General Electric Company

Peter F Corbett

Richard I Hartley

Fathy F Yassa

Sharbel E Noujaim

A method of transforming systolic arrays using bit-parallel arithmetic into arrays using digit-serial arithmetic is described. Digit-serial computation is an area-time efficient method of doing high-speed arithmetic calculations, having the advantage through appropriate choice of digit and word size of allowing throughput capacity to be matched to design needs. For a certain class of systolic arrays, however, digit-serial arithmetic allows a further very significant benefit, by transforming arrays in which processors are under-utilized into arrays with 100% processor utilization. As an example, converting a well-known band-matrix multiplication array to use digit-serial processing is calculated to give an improvement of more than three times in area-time efficiency.

Systolic array processors for reducing under-utilization of original

Conversion apparatus is used to convert digital data words to a digit-serial data format wherein digit bit-width is optimal for subsequent processing of the digital data words. Optimization is with regard to throughput efficiency, a measure of integrated circuit performance proportional to throughput rate of integrated circuitry and inversely proportional to the area of that integrated circuitry, comprising processing circuitry and attendant conversion circuitry.

Data format converters for use with digit-serial signals

Linear combining apparatus for digit-serial data performs addition, subtraction and comparison functions on a systolic basis. Signals are afforded the apparatus indicating the occurence of the most significant digits of the digit-serial signals being linearly combined.

Digit-serial linear combining apparatus

One type of transversal filter using digit-serial signals in its operation comprises a to-digit-serial converter for converting a succession of input data words received at its input port each to a respective succession of m-bit-wide digits supplied from its output port in order of progressively greater significance, m being a positive plural integer; a clocked delay line having an input tap connected for responding to the m-bit-wide digits supplied from the output port of the to-digit-serial converter and having at least one further tap for supplying a respective tap signal; and means for performing a weighted summation of the input signal to the clocked delay line and each tap signal from the clocked delay line, to generate a filter response in digit-serial format. Another type of transversal filter, which uses digit-serial signals in its operation, comprises a plurality, p in number, of parallel-to-digit-serial converters, each for generating a respective m-bit-wide digit-serial data stream by converting n-parallel-bit words in an input signal to the digital filter, m being a positive integer and n being the product of m and p; a plurality of tapped delay lines having respective input taps connected from respective ones of said parallel-to-digit-serial converters and each having at least one further tap; means for generating p different phases of filter response in digit-serial form by weighting and summing digital signals taken from respective taps on ones of the p tapped delay lines; and p digit-serial-to-parallel converters for converting, on a cyclic basis, the different phases of filter response to parallel-bit words in an output signal from the digital filter.

Digit-serial transversal filters

Increased performance of digital integrated circuits by processing with

Linear combining apparatus for digit-serial data performs addition, subtraction and comparison functions. The capability of performing addition or subtraction as the result of comparison permits non-restoring division to be done using a plurality of the linear combining apparatuses.

Digit-serial linear combining apparatus useful in dividers

A design methodology for digit serial architecture, especially for use in digital signal processing circuitry, includes a cell stack configuration incorporating a variable number of individual operation cells in conjunction with cap and control cells to provide power, control and timing signals. The arrangement employed permits the construction of cell libraries for silicon compilers from a small number of individual components and permits such compilers to generate chip fabrication masks for a plurality of fixed, but initially arbitrary digit size circuit designs.

Cell stack for variable digit width serial architecture

To-digit-serial converters for systems processing data in digit-serial

A digital multiplier for multiplying together W-bit digit-serial multiplier and multiplicand signals includes a combinational array of multiplier cells arranged in N rows and W columns. A digit-serial-in/parallel-out register supplies respective bits of each successive multiplicand signal to the W columns of the array, the N rows of which receive respective bits of each successive digit of the multiplier signal. After each earlier digit of the multiplier is processed, the carry and sum bits are forwarded without column shift and with one column shift, respectively, from the final row to the first row of multiplier cells. This scrolls the operation of the W-column-by-N-row multiplier cell array, allowing it to be used M times for each word of the multiplier signal, one for each of the M digits in a W-bit word of the multiplier signal. The sum bits from the final column of multiplier cells provide the minor product output signal of the digital multiplier in digit-serial format, as each digit of the multiplier signal is processed. In processing the final digit of the multiplier, the carry and sum bits are shifted differentially by one bit place and are conveyed by shift registers to a digit-serial final adder, the full sum output of which supplies the major product output signal of the digital multiplier in digit-serial form. Supplying the minor and major product output signals in parallel permits pipelined operation of the apparatus.

Bit-sliced digit-serial multiplier

A data shifter is constructed in monolithic integrated-circuit form essentially from three basic cells, namely: a first or A type of bit-slice cell with a multiplexer for selecting one of two inputs to a clocked output latch, a second or B type of bit-slice cell with a multiplexer for selecting one of two inputs to a cascaded pair of clocked latches, and a control cell for controlling the selection process in bit-slice cells arranged in a stack therewith. In addition where the order of the bits in each successive digit of the shifter output needs to be rotated, this can be accomplished using combinations of two further types of basic cells, namely: a braid-slice cell, and a braid-cap cell. These cells are rectangular and tile in a close-packed mosaic. The disclosure describes how to make a same set of basic cells that is adaptable for use both in left shifters and in right shifters.

Digit-serial shifters constructed from basic cells

A circuit for supplying safe logic zero and logic one signals to hardwired inputs of CMOS ICs comprises, at most, three field effect transistors, none of which have gates connected to either drain voltage V.sub.dd or source voltage V.sub.ss. The circuit has no external inputs and has two outputs, logic zero and logic one. The circuit has only one stable operating point and moves to this operating point from any initial condition. The circuit is safe and can enhance the reliability of ICs as it provides the same noise protection from voltages V.sub.ss and V.sub.dd for nodes connected to its output that an inverter provides for nodes connected to its output.

Safe logic zero and one supply for CMOS integrated circuits

A double precision, low-latency two's complement bit-serial multiplier operates on the fact that after both inputs have been fully read into the multiplier, the calculation has proceeded to such a stage that it may be completed with a single counter. The multiplier comprises a plurality of bit slices and an endcell connected in series. The serial bit streams of the operands are sampled by latches in each of the bit slices, and the sampled bit values are accumulated using (5,3) counters to generate partial sum output signals. The partial sum output signal for the last bit slice is the least significant word of the double precision product. The endcell comprises another (5,3) counter which accumulates propagated sum and carry output signals of the bit slices and generates the most significant word of the double precision product.

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Princeton, NJ, United States of America

Peter F Corbett