Interdigital Technology Corporation

Peter Edward Becker

Ryan Samuel Buchert

Sharif M Shahrier

Chayil S Timmerman

Robert A DiFazio

Muhammad U Fazili

Stephan Shane Supplee

Bin Li

Alexander Reznik

Jung-Lin Pan

John W Haim

John David Kaewell, Jr

Tonino Nasuti

Shane S Supplee

An apparatus and method for DFT processing using prime factor algorithm (PFA) on a selected number P of midamble chip values received by a CDMA receiver, where P has a plurality M of relatively prime factors F, and the DFT process is divided into M successive F-point DFT processes. The P data values are retrieved from a single input port memory and selectively permuted by a controller into parallel caches to optimize factoring with associated twiddle factors stored in parallel registers. The permuted inputs are factored in two or more parallel PFA circuits that comprise adders and multipliers arranged to accommodate any size F-point DFT. The outputs of the PFA circuits are processed by consolidation circuitry in preparation for output permutation of the values which are sent to memory for subsequent DFT cycles.

Optimized discrete fourier transform method and apparatus using prime factor algorithm

A wireless transmit receive unit (WTRU) recovers data from a plurality of data signals received as a received vector. The WTRU determines data of the received vector by determining a Cholesky factor of an N by N matrix and using the determined Cholesky factor in forward and backward substitution to determine data of the received data signals. The WTRU comprises an array of at most N scalar processing elements. The array has input for receiving elements from the N by N matrix and the received vector. Each scalar processing element is used in determining the Cholesky factor and performs forward and backward substitution. The array outputs data of the received vector.

User equipment and base station performing data detection using a scalar array

A receiver or an integrated circuit (IC) incorporated therein includes a fast Fourier transform (FFT)-based (or hybrid FFT-based) sliding window block level equalizer (BLE) for generating equalized samples. The BLE includes a noise power estimator, first and second channel estimators, an FFT-based chip level equalizer (CLEQ) and a channel monitor unit. The noise power estimator generates a noise power estimate based on two diverse sample data streams. The channel estimators generate respective channel estimates based on the sample data streams. The channel monitor unit generates a first channel monitor signal including truncated channel estimate vectors based on the channel estimates, and a second channel monitor signal which indicates an approximate rate of change of the truncated channel estimate vectors. The FFT-based CLEQ generates the equalized samples based on the noise power estimate, one-block samples of the first and second sample data streams, the channel estimates and the monitor signals.

Advanced receiver with sliding window block linear equalizer

A user equipment or base station recovers data from a plurality of data signals received as a received vector. The user equipment determines data of the received vector by determining a Cholesky factor of an N by N matrix and using the determined Cholesky factor in forward and backward substitution to determine data of the received data signals. The user equipment or base station comprises an array of at most N scalar processing elements. The array has input for receiving elements from the N by N matrix and the received vector. Each scalar processing element is used in determining the Cholesky factor and performs forward and backward substitution. The array outputs data of the received vector.

A circuit is capable of performing a complex division and dual complex multiplication. The complex division involves dividing a first complex value by a second complex value and the dual complex multiplication involves multiplying a third complex value by a fourth complex value and a fifth complex value by a sixth complex value. The circuit comprises a first input configured to receive the first and second complex values when the circuit is performing the complex division and the third and fourth complex values when the circuit is performing the dual complex multiplication. A second input is configured to receive the second complex value when performing the complex division and the fifth and sixth complex values when performing dual complex multiplication. A first output produces a result of complex multiplication of the third and fourth complex values when the circuit is performing the dual complex multiplication. A second output produces a result of the complex division of the first complex value divided by the second complex value when the circuit is performing the complex division and complex multiplication of the fifth complex value by the sixth complex value when performing the dual complex multiplication.

Dual use dual complex multiplier and complex divider

Multi-user detection (MUD) performance is optimized to eliminate redundant use of power during processing. An overbuilt A-matrix, i.e., a system response matrix, is provided. The overbuilt A-matrix uses all possible codes, e.g., all codes identified in a candidate code list (CCL) provided by blind code detection (BCD). The overbuilt A-matrix is passed to the MUD which extracts only those rows or columns required for codes that have actually been received, thus eliminating the need to recompute whitening matched filter (WMF) outputs that do not correspond to the actually received code.

Wireless communication method and apparatus for optimizing multi-user detection

An apparatus and method for data processing particularly useful in combining convolutions of the spreading code, scrambling code and channel response in order to construct a system transmission coefficient matrix, while maintaining the same circuit size and execution time relative to performing each convolution separately. One register for processing real channel response values and a second register for processing imaginary channel response values, are used for moving channel responses through the convolution. In place of multipliers, an optimized minimum number of adders connected in a pyramid configuration are used to perform the necessary multiplication of the codes, for simplicity of construction. By including the channel code transformation from binary representation to complex representation as part of the overall method, unnecessary adders are eliminated from the apparatus.

CDMA system transmission matrix coefficient calculation

A circuit performs complex division and dual complex multiplication. The circuit has a plurality of multipliers. Each of the plurality of multipliers is used in both the complex division and the dual complex multiplications. The circuit also has a plurality of components capable of adding and subtracting. Each adding and subtracting component is used during the complex division and the dual complex multiplication and switches between operation as an adder and a subtractor between performing the complex division and the dual complex multiplication. Preferred potential uses for the circuit are in a receiver of a user equipment or a base station. The circuit is used in a fast Fourier transform (FFT) based channel estimation or a FFT based data detection.

Growing community of inventors

Coatesville, PA, United States of America

Peter Edward Becker