Emc Corporation

Emc IP Holding Company LLC

Peter E Tolvanen

Qi Zhang

Qing Liu

Philippe Armangau

Miles Aram De Forest

David W Harvey

Alan Lee Taylor

Christopher Alan Seibel

David Haase

Nagapraveen Veeravenkata Seela

Paul Thomas McGrath

Dayanand Suldhal

Hongliang Tang

Henry Austin Spang, Iv

T David Evans

Gregory S Schaffer

Brahmadev Anand

Improved techniques for maintaining cache coherence in a consistent state are provided. These techniques implement a data storage system using a journaled mirrored cache that ensures that storage operations making up certain transactions be performed atomically, so that a system failure does not result in data loss. The improved techniques also allow for efficient communication of mirroring information.

Techniques for maintaining cache coherence by atomically processing groups of storage commands

A storage system uses a block-level file system to manage physical storage of data blocks of logical units, the file system being mounted on an owning one of a set of storage processors. The storage processors redirect received storage requests to the owning storage processor, and periodically the amount of redirection is evaluated. If the amount of redirection is higher than a threshold, then the file system is dismounted at the owning storage processor and mounted at another storage processor to reduce the amount of redirection.

Storage system with dynamic transfer of block file system ownership for load balancing

A method is used in managing ownership of logical volumes. A path to a logical volume is determined, where upper-layer software selects the path to the logical volume. Based on the selection of the path, ownership of the logical volume is assigned. Lower-layer software assigns ownership of the logical volume based on information received from the upper-layer software.

Managing ownership of logical volumes

A method is used in determining alternate paths in faulted systems. It is detected that a first processor has a problem accessing a target. The first processor has a first path to the target. An alternate path to the target is determined by identifying that a second processor has better access to the target than the first processor. The second processor has a second path to the target. Responsibility for I/O communication with the target is transferred from the first processor to the second processor. Responsibility for I/O communication with the target is transferred back to the first processor upon resolution of the problem.

Determining alternate paths in faulted systems

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Mendon, MA, United States of America

Peter E Tolvanen