Advanced Micro Devices Corporation

Legerity, Inc.

Peter E Sheldon

Paul G Schnizlein

Alan R Hendrickson

Alan F Hendrickson

Jacqueline E Mullins

A reset circuit that incorporates a battery monitor and watchdog timer in an integrated circuit is disclosed. A battery monitor having an output indicative of a charge state of a battery and a watchdog timer having an output indicative of an operational state of software being executed by the integrated circuit are connected to reset logic having a reset signal output, wherein the reset logic generates a reset signal on the reset signal output if either the battery monitor output or the watchdog timer output is active.

Integrated circuit reset incorporating battery monitor and watchdog timer

A digital cordless telecommunications unit that serves for communications when paired with a similar unit and connected with a network is disclosed. The unit receives analog receive voice signals and transmits analog transmit voice signals. In addition, the unit transmits digital baseband transmit signals and receives digital formatted baseband receive signals. The unit includes a baseband chip, as well as an audio functions circuit and a system control functions circuit. The audio functions circuit comprises an audio front end for receiving the analog receive voice signals and transmitting the analog transmit voice signals, and an adaptive differential pulse code modulator codec, connected to the audio front end, for converting the analog receive voice signals to the digital transmit signals and converting the digital formatted baseband receive signals to the analog transmit voice signals. The system control functions circuit comprises a microcontroller, connected to the codec, for controlling the baseband chip, a memory accessible by the microcontroller for storing control instructions, an interrupt controller connected to the microcontroller, a parallel port connected to the interrupt controller, a wake-up timer connected to the interrupt controller, a clock generator connected to the microcontroller, and a synchronous serial port connected to the interrupt controller.

Narrowband digital cordless telephone

A battery monitor with programmable voltage references. The battery monitor includes a comparator circuit connected to a battery for receiving a voltage level thereof and to a voltage reference circuit for receiving a at least one reference voltage generated thereby. A trim circuit is connected to the voltage reference circuit for adjusting the reference voltage(s) and generated by the voltage reference circuit. The comparator circuit compares the voltage level of the battery with the reference voltage(s) generates an output based on the relative value of the battery voltage compared to the reference voltage(s). The trim circuit is programmable and includes a microprocessor connected to a programmable register and a memory. The microprocessor obtains trim data from the memory and writes the trim data to the programmable register.

Battery monitor with software trim

Method and apparatus for providing a FSK data slicer for use in wireless telecommunications such as cordless telephones. The FSK data slicer is used by a receiver circuit in a wireless telecommunication device for converting an analog data signal to a digital data signal. Furthermore, the FSK data slicer responds to different mode of the analog data signal. The FSK data slicer includes a low-pass filter, a controller, a comparator, and an integrator. The low-pass filter receives the analog data signal for generating a median voltage, or slice voltage. Furthermore, the low-pass filter includes connectors to allow an external resistor to be serially connected between the filter input and the analog data signal and to allow an external capacitor to be connected in parallel with the slice voltage at the filter output. The bandwidth of the low-pass filter is controlled by the controller. The controller responds to specific intervals of the TDD frames, initial acquisition of data in the analog data signal, and known characteristics of the TDD frames and adjusts the low-pass filter bandwidth, accordingly. As a result, the low-pass filter drives the slice voltage only when it can do so accurately, and drives it strongly when the slice voltage will be very accurate. The comparator receives and compares the analog data signal and the slice voltage in order to produce a digital data signal. The digital data signal is then sent to the integrator, which over-samples each data bit of the digital data signal. The over-sampling is concentrated on the middle three quarters of each data bit, thereby ensuring the highest level of reliability.

Data slicer for demodulated binary FSK signals in a time division duplex

A circuit for generating a threshold voltage level from a time division duplex analog data signal. The circuit comprises a sample/hold circuit and an amplifier. The sample/hold circuit is arranged to sample the threshold voltage level during a reception interval and hold the threshold voltage level during a transmission interval. The amplifier includes an operational amplifier coupled to the sample/hold circuit for amplifying the analog data signal during a reception interval and amplifying the threshold voltage level during a transmission interval. A transconductance device is coupled to the operational amplifier, and a plurality of load legs are respectively coupled to a plurality of bias legs. A first selected pair of the respectively coupled load legs and bias legs is coupled to the transconductance device, and a second selected pair of the respectively coupled load legs and bias legs coupled to the output of the amplifier to provide the threshold voltage level.

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Austin, TX, United States of America

Peter E Sheldon