Sensors Unlimited

Peter E Dixon

Robert Rozploch

Navneet Masaun

Douglas Stewart Malchow

A low noise infrared photodetector has an epitaxial heterostructure that includes a photodiode and a transistor. The photodiode includes a high sensitivity narrow bandgap photodetector layer of first conductivity type, and a collection well of second conductivity type in contact with the photodetector layer. The transistor includes the collection well, a transfer well of second conductivity type that is spaced from the collection well and the photodetector layer, and a region of first conductivity type between the collection and transfer wells. The collection well and the transfer well are of different depths, and are formed by a single diffusion.

Method of forming an infrared photodetector

A focal plane array assembly includes a readout integrated circuit with a contact array surface, a photodiode array with a contact array surface facing the readout integrated circuit contact array surface, and an anisotropic conductive film disposed between contact array surfaces. The anisotropic conductive film includes conductive bodies that interconnect the photodiode array with the readout integrated circuit and an adhesive that couples the photodiode array to the readout integrated circuit.

Electrical interconnects for photodiode arrays and readout interface circuits in focal plane array assemblies

A camera comprises an image plane for capturing shortwave infrared wavelengths. The image plane captures only a portion of a shortwave infrared wavelength band, and excludes other wavelengths. A method of designing a camera is also disclosed.

Shortwave infrared camera with bandwidth restriction

Low noise hybridized detector using charge transfer

A focal plane array (FPA) comprising a photodiode array (PDA) and a read out integrated circuit (ROIC), wherein the FPA can include a plurality of conductive bumps that electrically couple PDA circuitry to ROIC circuitry. In an embodiment, an optically transparent lid can include a plurality traces electrically coupled to circuitry on the ROIC which can be used as a conductive path between the ROIC and external pads.

Read out integrated circuit input/output routing on permanent carrier

Provided is a focal plane array that includes an array of photodetectors, with each photodetector being in electrical communication with a corresponding one of an electrode of a read out integrated circuit. The array of photodetectors include an insulating layer, a blocking layer comprising at least one blind via, and an active layer formed between the insulating layer and the blocking layer. A first portion of the blocking layer transmits radiation having a first wavelength and reflects radiation having second wavelength that is lower than that of the first wavelength. A diameter of the at least one blind via is selected to allow radiation of the second wavelength to pass through the at least one blind via.

Perforated blocking layer for enhanced broad band response in a focal plane array

A focal plane array (FPA) including a photodiode array (PDA) and a read out integrated circuit (ROIC). The PDA can include a plurality of conductive through-vias extending through the PDA and electrically isolated from the PDA. The plurality of conductive through-vias can be electrically coupled to circuitry on the ROIC circuit side. The plurality of conductive through-vias can include I/O interconnects such as BGA or other flip-chip bump interconnects that replace conventional wire bond connections, thereby reducing area requirements for bond pads on the ROIC and providing full area coverage of the ROIC circuitry by the PDA bulk material. Embodiments may therefore eliminate wire bonds using bonding to a plurality of metal traces for routing of these interconnects. In an embodiment, an optically transparent lid can include a plurality traces electrically coupled to the plurality of conductive through-vias.

Focal plane array periphery through-vias for read out integrated circuit

A low noise infrared photo detector with a vertically integrated field effect transistor (FET) structure is formed without thermal diffusion. The FET structure includes a high sensitivity photo detector layer, a charge well layer, a transfer well layer, a charge transfer gate, and a drain electrode. In an embodiment, the photo detector layer and charge well are InGaAs and the other layers are InP layers.

Growing community of inventors

Princeton, NJ, United States of America

Peter E Dixon