International Business Machines Corporation

Tokyo Electron Limited

Peter E Biolsi

Samuel S Choi

Anthony K Stamper

Yun Han

Kevin MacKey

Laurie M Krywanczyk

Gregory S Jankowski

Lawrence Alfred Clevenger

Theodorus E Standaert

Daniel C Edelstein

Alok Ranjan

Merritt Funk

Vincent James McGahay

William J Cote

Michael Wayne Lane

Andrew W Metz

Matthew S Angyal

Habib Hichri

Daniel Joseph Prager

William C Wille

Jeffrey R Marino

Ken Kobayashi

Bernd E Kastenmeier

Allan Ward Upham

Tomoyuki Oishi

Shuhei Ogawa

Ryukichi Shimizu

John Fritche

Allan Ibm United Kingdom Limited Upham

A method of processing a substrate that includes: performing a cyclic plasma etch process including a plurality of cycles, each of the plurality of cycles including: etching a patterning layer including a polycrystalline semiconductor material to form or extend a recess by exposing the substrate to a first plasma, the substrate including an oxide layer, the patterning layer formed over the oxide layer, exposing the substrate to a second plasma, the second plasma including dihydrogen, and extending the recess by exposing the substrate to a third plasma, the second plasma being different from the first plasma and the third plasma.

Etching of polycrystalline semiconductors

A method which includes providing a substrate having a source/drain region and an etch stop layer on the source/drain region. A plasma etching process is performed using an etching gas that removes the etch stop layer and forms a sacrificial oxide capping layer on the source/drain region. The sacrificial oxide capping layer is then from the source/drain region.

Sacrificial capping layer for contact etch

A method for etching on a semiconductors at the back end of line using reactive ion etching. The method comprises reduced pressure atmosphere and a mixture of gases at a specific flow rate ratio during plasma generation and etching. Plasma generation is induced by a source radio frequency and anisotropic etch performance is induced by a second bias radio frequency.

Methods of manufacturing semiconductor structures using RIE process

The invention provides a systems and methods for creating Double Pattern (DP) structures on a patterned wafer in real-time using Dual Pattern Contact-Etch (DPCE) processing sequences and associated Contact-Etch-Multi-Input/Multi-Output (CE-MIMO) models. The DPCE processing sequences can include one or more contact-etch procedures, one or more measurement procedures, one or more contact-etch modeling procedures, and one or more contact-etch verification procedures. The CE-MIMO model uses dynamically interacting behavioral modeling between multiple layers and/or multiple contact-etch procedures. The multiple layers and/or the multiple contact-etch procedures can be associated with the creation of lines, trenches, vias, spacers, contacts, and gate structures that can be created during Double Patterning (DP) procedures.

Contact processing using multi-input/multi-output (MIMO) models

Methods for sealing an organic ILD layer and a metal layer after an etching step. The method includes etching through an ILD layer and leaving a remaining portion of an underlying metal layer cap, maintaining the device in an inert gas, and depositing at least a portion of a liner into the opening to seal the ILD layer and the metal layer. Subsequent processing may include formation of a via by etching through the portion of the liner and the remaining portion of the cap layer, and depositing a metal.

Interlevel dielectric layer and metal layer sealing

Methods of etching a dielectric layer and a cap layer over a conductor level to open a via to the conductor. The methods include the provision of tetrafluoro methane (CF) in a photoresist strip. In addition, the methods may provide an increased amount of tetrafluoro methane (CF) in a dielectric layer etch, and trifluoro methane (CHF) in a cap layer etch. The invention provides higher yield, more predictable etch rates, faster processing, and removes the need for an ash step.

Via reactive ion etching process

This invention relates to the manufacture of dual damascene interconnect structures in integrated circuit devices. Specifically, a method is disclosed for forming a single or dual damascene structure in a low-k dielectric thin film utilizing a planarizing material and a diffusion barrier material. In a preferred dual damascene embodiment of this method, the vias are formed first in the dielectric material, then the planarizing material is deposited in the vias and on the dielectric material, and the barrier material is deposited on the planarizing material. The trenches are then formed lithographically in the imaging material, etched through the barrier material into the planarizing material, and the trench pattern is transferred to the dielectric material. During and following the course of these etch steps, the imaging, barrier and planarizing materials are removed. The resultant dual damascene structure may then be metallized. With this method, the problem of photoresist poisoning by the interlevel dielectric material is alleviated.

Method for forming damascene structure utilizing planarizing material coupled with diffusion barrier material

A method of forming a damascene structure, and the structure so formed, using a sacrificial conductive layer to provide a uniform focus plane for the photolithography tool during formation of circuit features. In particular, a metal layer is provided between the insulative layer and the photoresist, upon which the capacitive sensors of the photolithography tool focus during the formation of the circuit features, namely, troughs and vias.

Damascene structure using a sacrificial conductive layer

A method of forming a damascene structure using a sacrificial conductive layer to provide a uniform focus plane for the photolithography tool during formation of circuit features. In particular, a metal layer is provided between the insulative layer and the photoresist, upon which the capacitive sensors of the photolithography tool focus during the formation of the circuit features, namely, troughs and vias.

Method of forming a damascene structure using a sacrificial conductive layer

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Essex Junction, VT, United States of America

Peter E Biolsi