Altera Corporation

International Business Machines Corporation

Northern Telecom Limited

Peter Douglas Bain

Peter Duncan Shipton

Kerry S Veenstra

Peter Wiebe Burka

Graham Alan Chapman

Aaron Ferrucci

Charles Robert Gracie

Timothy Allen

Dan Heidinga

A tool for inter-process communication in a multi-tenant environment. The tool creates an advertisement file for each tenant of a plurality of tenants. The tool locks a plurality of synchronization files prior to incrementing a semaphore, wherein the plurality of synchronization files correspond to the plurality of tenants, and wherein locking the plurality of synchronization files ensure that the semaphore is only decremented once per tenant. The tool searches for a response file corresponding to a specific tenant, wherein the response file includes metadata related to an information channel for communication with the specific tenant and information depicting a communication protocol used corresponding to the specific tenant. The tool unlocks the plurality of synchronization files. The tool establishes a connection, wherein the connection comprises an encrypted communication channel between the specific tenant and the attachment process mediated by a daemon.

Inter-process communication in a multi-tenant environment

Aspects of the present invention provide devices that count for an application thread levels of critical sections of program code, and in response to a program exception in the application thread that is deferrable and a non-zero count of the levels of critical sections, execute a remainder of program code within the critical sections of program code.

Programming language runtime deferred exception handling

Embodiments of the present invention provide memory optimization by phase-dependent data residency. Application programs are profiled a priori or in real time for temporal memory usage. Memory regions such as initialization data are proactively removed from memory when the application transitions to a new phase. A hypervisor monitors application activity and coordinates the removal of memory regions that are no longer needed by the application. Additionally, memory regions that are anticipated to be needed in the future are proactively preloaded.

Memory optimization by phase-dependent data residency

A method, executed by a computer, for inter-process communication in a multi-tenant environment includes creating an advertisement file for each tenant, determining that a semaphore is greater than zero, searching for a response file, and decrementing the semaphore. Detecting the response file may enable the specific tenant to establish a connection with an attachment process, and as a result, the semaphore may be reset to a value of zero. In one embodiment, a plurality of synchronization files are locked prior to incrementing the semaphore and unlocked in response to detecting the response file. Another method includes counting the targets to provide a target count, incrementing a semaphore to the target count, creating a response file, and establishing a connection with the specific target. A computer program product and computer system corresponding to the methods are also disclosed herein.

Establishing connections in a multi-tenant environment

A method for efficiently computing a hash value for a string is disclosed. In one embodiment, such a method includes receiving an original string comprising multiple characters. The method computes an original hash value for the original string. The method produces an updated string by performing at least one of the following updates on the original string: adding leading/trailing characters to the original string; removing leading/trailing characters from the original string, and modifying characters of the original string while preserving the length of the original string. The method then computes an updated hash value for the updated string by performing at least one operation on the original hash value, wherein the at least one operation takes into account the updates that were made to the original string. A corresponding apparatus and computer program product are also disclosed.

Efficient string hash computation

A method to enable communication between software processes includes initiating a plurality of processes, the processes including both attachment processes and target processes. A single semaphore is created and initialized for use by the plurality of processes such that each of the target processes wait on the semaphore. An attachment process writes a message file, identifying a specific target process, to a location accessible by the target processes. The attachment process then increments the semaphore by the number of target processes, thereby unblocking the target processes and allowing them to check the message file. When the specific target process determines that the message file is intended for that target, a connection is established between the attachment process and the specific target process. The attachment process then decrements the semaphore to zero to block the target processes. A corresponding computer program product and apparatus are also disclosed herein.

Interprocess communication using a single semaphore

Methods and apparatus are provided for more efficiently generating logic for implementing Exclusive OR (XOR) expressions. In one example, multiple centroids are generated and associated with main equations. Both the main equations and centroids are XOR expressions. In particular examples, main equations are associated with centroids that are closest in distance. Centroids can be modified to better match an associated subset of main equations. Centroids are generated and associated until the main equations are expressed as centroids and residue.

Increasing logic efficiency for exclusive OR (XOR) expressions

Circuits, methods, and apparatus for FIFO memories made up of multiple local memory arrays. These embodiments limit the number and length of interconnect lines that are necessary to join two or more local memory arrays into a single, larger functional unit. One exemplary embodiment of the present invention provides a FIFO made up of a number of FIFO sub-blocks connected in series. Each FIFO sub-block includes local read and write address counters such that read and write addresses are not bused between the FIFO sub-blocks.

Distributed FIFO

Methods and apparatus are provided for more efficiently computing error checking codes such as cyclic redundancy checks (CRCs). Based on particular characteristics of CRCs, an input sequence is intelligently divided into a series of subsequences. Each subsequence gets selected bits from the input sequence. The error checking code is calculated on each subsequence. The results are bit-interleaved and an error checking code is calculated over this interleaved result to obtain the error checking code over the entire sequence.

Methods and apparatus for error checking code computation

If an input word bit includes overhead data, the input word bit is ignored. If the input word bit includes non-overhead data and the corresponding bit position in a first buffer is empty, the non-overhead data is stored in the corresponding bit position in the first buffer, and the corresponding bit position in the first buffer is marked as full. Otherwise, the non-overhead data is stored in the corresponding bit position in a second buffer, and the corresponding bit position in the second buffer is marked as full. When all bit positions in the first buffer are marked as full, the data is shifted out of the first buffer, rotated to be in data arrival sequence, and made available for further processing. Then, the data in the second buffer is transferred to the first buffer, and the bit positions in second buffer are reset to be marked as empty.

Method and apparatus for processing communication protocol frame input

An apparatus and method for performing multiple exclusive OR (XOR) operations using standard binary multiplication circuitry to create multiple XOR expressions simultaneously. The method and apparatus include a multiplication circuit to generate a product result by performing a multiplication between a multiplier and a multiplicand. A selection circuit is then used to break down the product result into a plurality of partial product sub-expressions. An XOR gate is provided to generate a final expression from one or more of the plurality of partial product sub-expression. The present invention is suited for performing calculations involving a large number of XOR operations with various combinations of product terms, such as cyclical redundancy check calculations.

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Ottawa, Canada

Peter Douglas Bain