Analog Devices,inc.

Peter Derounian

Scott Gregory Bardsley

Franklin Marshall Murden, Ii

Brad Porcher Jeffries

Eric John Siragusa

Matthew D McShea

Reuben Pascal Nelson

Ziwei Zheng

Oscar Sebastian Burbano

An agile frequency synthesizer with dynamic phase and pulse-width control is disclosed. In one aspect, the frequency synthesizer includes a count circuit configured to modify a stored count value by an adjustment value. The frequency synthesizer also includes an output clock generator configured to generate an output clock signal having rising and falling edges that are based at least in part on the stored count value satisfying a count threshold. The count circuit is further configured to alter at least one of the period or phase of the output clock signal based at least in part on modifying an adjustment rate of the count circuit.

Frequency synthesizer with dynamic phase and pulse-width control

In one example implementation, the present disclosure provides a direct current (DC) restoration circuit for restoring the DC component of a synchronization signal provided over an alternating current (AC) coupled link from a transmitting circuit to a receiving circuit. During a period of inactivity in the synchronization signal, the synchronization signal may experience a drift towards the common mode, and may affect the ability for the synchronization signal to properly trigger the receiving circuit. The DC restoration circuit is configured to hold the synchronization signal steady during the period of inactivity, and allow the AC component of the synchronization signal pass through to the receiving circuit during the period of activity to alleviate the problem of baseline drift in the synchronization signal.

DC restoration for synchronization signals

A clock shifter circuit may receive a input clock in a first voltage domain and may generate a level-shifted output clock in a second voltage domain. The circuit may include a cross-coupled pair of transistor switches and a pair of capacitors. Each switch may have a drain coupled to one of the capacitors, a source coupled to a circuit supply voltage, and a gate coupled to the other capacitor. One capacitor may receive a true input clock version, while the other may receive a complement version. Each capacitor, in an alternating manner, may activate an opposing transistor switch to charge its capacitor during an active phase of its respective input clock. The circuit may generate the output clock from an output node connected between one of the transistor switches and its capacitor. The output clock may drive a load directly coupled to the output node.

System for a clock shifter circuit

Circuits and methods are introduced to allow for timing relationship between a clock signal and a synchronization signal to be observed. The observations may include observing the timing relationship between a capture edge of the clock signal and a transition of the synchronization signal. Based on the observations the timing of the synchronization signal transition may be adjusted. Observing the timing relationship may include providing a delayed synchronization signal and a delayed clock signal. The delayed synchronization signal may provide what happens before the capture edge of the clock signal. The delayed clock signal may provide what happens after the capture edge of the clock signal.

Clock signal synchronization

One embodiment relates to an apparatus configured to cancel charge injected on a node of a differential pair of nodes. A dummy circuit element can inject charge on an inverted node to cancel charge injected on a non-inverted node by a switch when the switch is switched off. In addition, another dummy circuit element can inject charge on the non-inverted node to cancel charge injected on the inverted node by another switch when the other switch is switched off. These dummy circuits elements can be cross-coupled.

Differential charge reduction

An analog-to-digital converter includes a plurality of sequentially cascaded stages, each stage including an amplifier and four copies of a circuit block including a flash and capacitors, in which the four copies of the circuit block operate interleavingly in a respective sample mode, pre-gain mode, gain mode, and reset mode of the circuit block, the copies of the circuit block in the sample mode, pre-gain mode, and reset mode are decoupled from the amplifier, and the copy of the circuit block in the gain mode is coupled to the amplifier to produce an output for a next following stage.

Pipelined analog-to-digital converter

Apparatus and methods for pipelined analog-to-digital conversion are disclosed. In some embodiments, a pipeline analog-to-digital converter includes a plurality of multiplying digital-to-analog converter (MDAC) stages coupled in cascade. At least one of the MDAC stages includes two or more flash ADCs connected in parallel, operating alternately to generate digital signals from an analog input voltage. In one embodiment, the flash ADCs provide the digital signals in an alternating manner to a capacitor block that receives a delayed analog input voltage. In another embodiment, the at least one MDAC may include two or more capacitor blocks, each of which is associated with a respective one of the flash ADCs, forming two or more sets of a flash ADC and a capacitor block. In yet another embodiment, the at least one MDAC also include three or more capacitor blocks, each of which can be randomly selected for one of the flash ADCs.

Apparatus and method for pipelined analog to digital conversion

Apparatus and methods for pipelined analog-to-digital conversion are disclosed. In some embodiments, a pipelined analog-to-digital converter includes a control and correction circuit; and a plurality of MDAC stages. At least one of the MDAC stages includes: an MDAC input to receive an analog input voltage; and a dual latch flash ADC comprising one or more dual latch comparators. At least one of the dual latch comparators includes: a pre-amplifier having an input coupled to the MDAC input, and an output; a demultiplexer having an input coupled to the output of the pre-amplifier, a first output, and a second output; a first latch having an input coupled to the first output of the demultiplexer, wherein the first latch may generate a first digital signal; and a second latch having an input coupled to the second output of the demultiplexer, wherein the second latch may generate a second digital signal.

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Greensboro, NC, United States of America

Peter Derounian