National Semiconductor Corporation

Samsung Electronics Co., Ltd.

Poa Sana Liquidating Trust

Peter Deane

Luu Thanh Nguyen

William Paul Mazotti

Bruce Carlton Roberts

Ken Pham

Jia Liu

Peter B Johnson

Peter Smeys

Albert Z H Wang

Chen H Tsay

John P Briant

Michael R Nelson

Janet E Townsend

Yibing Michelle Wang

Ilia Ovsiannikov

Roger William Clarke

Christopher James Smith

Haryanto Chandra

Brian Huss

Todd Thyes

John Rukavina

Glenn Woodhouse

Hsin-Ho Wu

Reda R Razouk

Yongseon Koh

Stephen Gee

Cade Murray

Chen-Hui Tsay

Hau Thanh Nguyen

Euan P Livingston

Stephen Jacob

Peter Johnson

An apparatus and a method are provided. The apparatus includes a light source configured to project light in a changing pattern that reduces the light's noticeability; collection optics through which light passes and forms an epipolar plane with the light source; and an image sensor configured to receive light passed through the collection optics to acquire image information and depth information simultaneously. The method includes projecting light by a light source in a changing pattern that reduces the light's noticeability; passing light through collection optics and forming an epipolar plane between the collection optics and the light source; and receiving in an image sensor light passed through the collection optics to acquire image information and depth information simultaneously.

Apparatus for and method of illumination control for acquiring image information and depth information simultaneously

An apparatus and method for determining a distance to an object using a binary, event-based image sensor. In one aspect, the image sensor includes memory circuitry and address decode circuitry. In one aspect, activation of a photodiode of the image sensor array by receipt of one or more photons is able to be used directly as an input to logic circuitry. In one embodiment, the image sensor includes photodiodes operating in an avalanche photodiode mode or Geiger mode. In one embodiment, the imaging sensor includes photodiodes operating as thresholded integrating pixels. The imaging sensor can be fabricated from one or more substrates having at least a first and a second voltage portion.

High resolution, high frame rate, low power image sensor

Using the same image sensor to capture a two-dimensional (2D) image and three-dimensional (3D) depth measurements for a 3D object. A laser point-scans the surface of the object with light spots, which are detected by a pixel array in the image sensor to generate the 3D depth profile of the object using triangulation. Each row of pixels in the pixel array forms an epipolar line of the corresponding laser scan line. Timestamping provides a correspondence between the pixel location of a captured light spot and the respective scan angle of the laser to remove any ambiguity in triangulation. An Analog-to-Digital Converter (ADC) in the image sensor operates as a Time-to-Digital Converter (TDC) to generate timestamps. When the epipolar line is misaligned or curved, multiple TDC arrays acquire timestamps of multiple pixels (in multiple rows) substantially simultaneously. Multiple timestamp values are reconciled to obtain a single timestamp value for a light spot.

Increasing tolerance of sensor-scanner misalignment of the 3D camera with epipolar line laser point scanning

Various apparatuses and methods for forming integrated circuit packages are described. One aspect of the invention pertains to an integrated circuit package in which one or more integrated circuits are embedded in a substrate and covered with a layer of photo-imageable epoxy. The substrate can be made of various materials, including silicon, quartz and glass. An integrated circuit is positioned within a cavity in the top surface of the substrate. The epoxy layer is formed over the top surface of the substrate and the active face of the integrated circuit. An interconnect layer is formed over the epoxy layer and is electrically coupled with the integrated circuit.

Integrated circuit micro-module

A two terminal ESD protection structure formed by an alternating arrangement of adjacent p-n-p-n-p semiconductor regions provides protection against both positive and negative ESD pulses. When an ESD pulse appears across the two terminals of the ESD protection structure, one of the inherent n-p-n-p thyristors is triggered into a snap-back mode thereby to form a low impedance path to discharge the ESD current. Some embodiments of the ESD protection structure of the present invention have an enhanced current handling capability and are formed by combining a number of standard cells. The standard cells include a corner cell, a center cell and an edge cell which are arranged adjacent each other to form an ESD protection structure which provides for current flow from across many locations therein. Some embodiments of the ESD protection structure of the present invention include a network consisting of a pair of current sources, e.g. back-to-back zener diodes, each connected in series with a resistor to control the trigger voltage of the ESD protection structure.

Dual-directional electrostatic discharge protection method

A two-terminal ESD protection structure formed by an arrangement of five adjacent semiconductor regions (, and) of alternating conductivity type provides protection against both positive and negative ESD voltages. The middle semiconductor region electrically floats. When the two terminals (A and K) of the ESD protection structure are subjected to an ESD voltage, the structure goes into operation by triggering one of its two inherent thyristors (and) into a snap-back mode that provides a low impedance path through the structure for discharging the ESD current.

Dual-directional electrostatic discharge protection device

Various apparatuses and methods for forming integrated circuit packages are described. One aspect of the invention pertains to a method for forming a microsystem and one or more passive devices in the microsystem. Layers of epoxy are sequentially deposited over a substrate to form multiple planarized layers of epoxy over the substrate. The epoxy layers are deposited by spin coating. At least some of the epoxy layers are photolithographically patterned after they are deposited and before the next epoxy layer is deposited. An integrated circuit having multiple I/O bond pads is placed on an associated epoxy layer. At least one conductive interconnect layer is formed over an associated epoxy layer. A passive component is formed within at least one of the epoxy layers. The passive component is electrically coupled with the integrated circuit via at least one of the interconnect layers. Multiple external package contacts are formed. The integrated circuit is electrically connected to the external package contacts at least partly through one or more of the conductive interconnect layers. Various embodiments pertain to apparatuses that are formed by performing some or all of the aforementioned operations.

Various methods for forming an integrated circuit micro-module are described. In one aspect of the invention, layers of an epoxy are sequentially deposited over a substrate to form planarized layers of epoxy over the substrate. The epoxy layers are deposited using spin coating. At least some of the layers are photolithographically patterned after they are deposited and before the next epoxy layer is deposited. Openings are formed in at least some of the patterned epoxy layers after they are patterned and before the next epoxy layer is deposited. An integrated circuit is placed within one of the openings. At least one of the epoxy layers is deposited after the placement of the integrated circuit to cover the integrated circuit. At least one conductive interconnect layer is formed over an associated epoxy layer. Multiple external package contacts are formed. The integrated circuit is electrically connected with the external package contacts at least in part through one or more of the conductive interconnect layers.

Various apparatus and methods for improving the dissipation of heat from integrated circuit micro-modules are described. One aspect of the invention pertains to an integrated circuit package with one or more thermal pipes. In this aspect, the integrated circuit package includes multiple layers of a cured, planarizing dielectric. An electrical device is embedded within at least one of the dielectric layers. At least one electrically conductive interconnect layer is embedded within one or more of the dielectric layers. A thermal pipe made of a thermally conductive material is embedded in at least one associated dielectric layer. The thermal pipe thermally couples the electrical device with one or more external surfaces of the integrated circuit package. Various methods for forming the integrated circuit package are described.

In one aspect, an integrated circuit package composed of a plurality of immediately adjacent stacked layers of cured, planarizing, photo-imageable dielectric is described. At least one interconnect layer is provided between a pair of adjacent dielectric layers. An integrated circuit is positioned within one or more of the dielectric layers such that at least one of the dielectric layers extends over the active surface of the integrated circuit. The integrated circuit is electrically coupled with I/O pads on a surface of the package at least in part through the interconnect layer or electrically conductive vias. In particular embodiments, the package can include thermal pipes, a heat sink, multiple integrated circuits, interconnect layers, conductive vias that electrically connect different components of the package and/or passive devices. In some specific embodiments, the dielectric layers are formed from a suitable epoxy such as SU-8 type. In a method aspect of the invention, the dielectric layers may be formed using a spin-on coating approach and patterned using conventional photolithographic techniques.

Various apparatuses and methods for forming integrated circuit packages are described. One aspect of the invention pertains to a wafer level method for packaging micro-systems. A substrate prefabricated with metal vias can be provided. The substrate can also be made by forming holes in a substrate and electroplating an electrically conductive material into the holes to form the vias. Multiple microsystems are formed on a top surface of the substrate. Each microsystem is formed to include multiple layers of planarizing, photo-imageable epoxy, one or more interconnect layers and an integrated circuit. Each interconnect layer is embedded in an associated epoxy layer. The integrated circuit is positioned within at least an associated epoxy layer. The interconnect layers of the microsystems are formed such that at least some of the interconnect layers are electrically coupled with one or more of the metal vias in the substrate. Molding material is applied over the top surface of the substrate and the microsystems to form a molded structure. Portions of the substrate can be removed. The molded structure can be singulated to form individual integrated circuit packages. Each of the integrated circuit packages contains at least one microsystem. Various embodiments involve forming conductive pads on the top surface of the substrate instead of the metal vias.

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Moss Beach, CA, United States of America

Peter Deane