Hewlett-packard Development Company, L.p.

Hewlett Packard Enterprise Development LP

Peter David Maroni

Daniel Alan Berkram

Dacheng Zhou

Erin Hallinan

Gregg Bernard Lesartre

Jonathan P Lotz

Justin Allan Coppin

James Donald Regan

Thomas N Indermaur

John E Tillema

John E Tilleman

James Kwok Yue Wai

Michael Joseph Howe

Robert E Wessel

A method of initializing an application-specific integrated circuit (ASIC), the method including reading, by a boot microcode engine integrated with the ASIC, microcode from an electrically programmable non-volatile memory (EP-NVM) integrated on a same die as the ASIC. The method further includes writing the microcode onto internal memories of a micro-controller of the ASIC and initializing the micro-controller by the boot microcode engine. The method also includes loading, by the micro-controller, a full boot image from an additional storage device distinct from the EP-NVM onto the internal memories of the micro-controller and initializing the ASIC by the micro-controller based on the full boot image.

Electrically programmable application-specific integrated circuit initialization engine

Systems and methods for performing data transfer between first and second electrical devices are provided. One method may include electrically coupling the first electrical device to a first electrical-optical (E-O) device via a first plurality of electrical lanes, electrically coupling the second electrical device to a second E-O device via a second plurality of electrical lanes, optically coupling the first and second E-O devices via a plurality of optical lanes, and transferring data therebetween via a first optical lane. The method may include monitoring one or more parameters associated with an optical transmitter of the first optical lane, and comparing each parameter to a respective threshold. Responsive to the comparison, the method includes commencing transfer of data between the first and second E-O devices via a second optical lane, and terminating transfer of the data between the first and second E-O devices via the first optical lane.

Data transfer between electrical-optical devices

A programmable integrated circuit may include logic, signal select hardware, programmable signal analysis hardware, an embedded microcontroller, and a hardware interface. The logic performs one or more functions and outputs a plurality of signals. The signal select hardware selects one or more of the signals output from the logic. The programmable signal analysis hardware analyzes the selected signals to produce diagnostic data. The embedded microcontroller receives the diagnostic data from the programmable signal analysis hardware and may reconfigure the logic based on the diagnostic data. The hardware interface connects the programmable signal analysis hardware and the embedded microcontroller to transport the diagnostic data.

Programmable integrated circuit with internal diagnostic hardware

A technique includes determining a first phase delay associated with communication of a bit pattern having a first bit transition frequency over a communication channel; and determining a second phase delay associated with communication of a bit pattern having a second bit transition frequency greater than the first bit transition frequency over the communication channel. The technique includes regulating a compensation applied to a signal received from the communication channel based at least in part on a difference of the first and second phase delays.

Phase delay difference-based channel compensation

In at least some embodiments, an electronic device includes a processor and a memory coupled to the processor. The electronic device also includes a serial communication link controller coupled to the processor, the serial communication link controller supporting dynamic reconfiguration of a plurality of communication link bundles. The serial communication link controller receives an input clock and generates first and second clock signals based on the input clock, the first and second clock signals having different clock rates and being provided to each of a plurality of communication link bundles.

Clock signals for dynamic reconfiguration of communication link bundles

During a calibration process, a data input signal is sampled using each of plural receiver equalization setting. For each of the receiver equalization settings, a respective offset-data error-rate is measured. Based on the offset-data error-rate measurements, an equalizer setting is selected for use during normal non-calibration operation of the receiver.

Receiver calibration using offset-data error rates

A system and method for detecting electrical idle in a receiver is disclosed herein. A receiver includes a differential receiver, an analog idle detector, and a first filter. The differential receiver receives a variable rate differential signal. The analog idle detector is coupled to the differential receiver. The analog idle detector provides a first idle signal that erroneously identifies a differential signal electrical idle state. The first filter is coupled to the analog idle detector. The first filter processes the first idle signal and generates a second idle signal lacking the idle state errors of the first idle signal. The first filter provides the second idle signal to receiver control logic that controls signal reception.

Method and apparatus for detecting electrical idle

A system and method for loopback self testing. A system includes a host device and an endpoint device. The host device transmits unencoded test symbols. The endpoint device loops back the unencoded test symbols to the host device. The host device drives at least some bits of each unencoded test symbol onto host device data signals and drives at least some bits of each unencoded test symbol onto host device control signals.

Method and apparatus for loopback self testing

Computer-readable media and methods for designing semiconductor artwork. Basic building blocks, or leaf cells, of an existing piece of semiconductor artwork are transferred to a new piece of semiconductor artwork in order to streamline the design process of the new design. In addition to being transferred, the position of METAL 1 layers within the leaf cells are also analyzed to avert possible design rule violations in the new design.

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Windsor, CO, United States of America

Peter David Maroni