Hitachi Global Storage Technologies Netherlands B.v.

Vishay-siliconix

Peter Dang

Cherngye Hwang

Eric Wayne Flint

Yongjian Sun

Hamza Yilmaz

Mohamed N Darwish

Kyle Terrill

Brian Rodrick York

Jila Tabib

John Huang

Daryl J Pocker

Jorge Goitia

Eduardo Torres Mireles

Wharton McDaniel

An assembly, apparatus and method for fabricating a structural element of a hard disk drive air bearing. The method and apparatus provide an improved protective layer, an improved structural element consisting of a single layer of structural material, and a method consisting of applying the improved protective layer, applying a uniform layer of structural material, applying a resist layer, etching the structural material layer, and removing the resist layer.

Assembly, apparatus and method for fabricating a structural element of a hard disk drive air bearing

A shaper for shaping an ion beam and that can be used for both deposition and etching is described. The shaper includes a plate that is placed between an ion beam grid and an ion beam source. The plate covers holes in the grid, and is shaped and dimensioned such that the plate does not partially cover any holes in the grid that are directly adjacent to the plate. A hole is configured to mount the shaper at a center of the grid and at least one other hole is configured to secure the shaper to the grid to prevent the shaper from rotating relative to the grid. A center mount portion covers holes in the grid. The plate has two axes of reflection symmetry. The uniformity of both deposition and etching is improved.

Symmetrical shaper for an ion beam deposition and etching apparatus

A hard disk drive slider comprises an overcoat layer, which covers an air-bearing surface of the slider. The overcoat covers an exposed surface of a tunneling magnetoresistance transducer. An adhesion layer is coupled with the overcoat layer and the air-bearing surface. The adhesion layer comprises a compound of nitrogen. The compound of nitrogen reduces noise in read data from the tunneling magnetoresistance transducer.

Insulator barrier for noise reduction of a TMR magnetic transducer

A power FET and a replica FET on a semiconductor chip coupled to a logic control circuit on a second semiconductor chip within a single housing. A power FET and a scaled down replica of the power FET are disposed on a semiconductor chip. The power FET is used as a switch to couple a DC power source to a load. A fraction of the power FET drain current passes through the replica FET and an external resistance. When the voltage across the external resistance exceeds a maximum value based upon the maximum allowable power FET drain current, the logic control circuit enters into a pulsed gate (PG) mode of operation. The first step in the PG mode is to switch both FETs into a non-conducting state for a predefined period of time. After this time period, a ramp voltage applied between gate and source of both FETs will switch them back into a current conducting state while holding the power FET drain current below its upper limit in the presence of a high capacitance load. If the voltage across the external resistance increases above the maximum, the PG mode of operation continues. PG mode of operation ceases and normal operation follows when the external resistance voltage remains below the established maximum. The combination of predefined nonconducting time and maximum drain current ensures operation of the power FET below maximum power dissipation limits. The PG mode of operation eliminates the need for additional temperature and thermal control circuits.

Current limiting technique for hybrid power MOSFET circuits

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San Jose, CA, United States of America

Peter Dang