International Business Machines Corporation

Peter Dana Driever

Kenneth J Oakes

Steven G Glassen

Harry M Yudenfriend

Peter Grimm Sutton

Christoph Raisch

Peter Kenneth Szwed

Marco Kraemer

Donald W Schmidt

Bernd Nerz

Frank Siegfried Lehnert

Charles W Gainey, Jr

Matthias Klein

Elpida Tzortzatos

Thomas B Mathias

Christian Jacobi

Jonathan D Bradbury

Brenton F Belmar

David Harold Surman

Steven N Goss

Sascha Junghans

Georgette L Kurdt

Andrew W Piechowski

Kenneth James Oakes

Steven Gardner Glassen

Harry Yudenfriend

Richard K Errickson

Dennis J Dahlen

Jeffrey William Josten

Craig A Bickelman

Ambrose Verdibello

Brian K Wade

Michael L Greenblatt

Seth E Lederer

John Charles Nagy

Omkar Ulhas Javeri

Charles Gainey

Thomas Brian Mathias

Charles Gainey Jr

Jr Charles Gainey

A vector entry of a signaling vector is registered to a buffer summary group. The buffer summary group includes one or more summary indicators for one or more buffers assigned to the buffer summary group. A command is processed that sets a vector indicator in the vector entry and based on setting the vector indicator in the vector entry, a summary indicator of the one or more summary indicators is set in the buffer summary group.

Vector processing employing buffer summary groups

A method, computer program product, and system include a processor(s) issues an instruction that includes processing core information that includes locations of processing cores of the computing system (logical cores and/or physical cores), and an operator selection. The processor(s) sets security parameters for information returned by the instruction which is topological information for mapping of the logical cores to the physical cores. The processor(s) obtains the topological information and utilizes an operating system to map the logical cores to the physical cores.

Accessing topological mapping of cores

A processor receives an interrupt signal. The interrupt signal is received with an interrupt target ID identifying a target processor for handling the interrupt signal. The processor is a target of the interrupt signal directly. A check is made as to whether the processor is the target processor identified by the interrupt target ID. The checking includes performing a comparison of the interrupt target ID with a current interrupt target ID assigned to the processor. Based on the checking being successful, the interrupt signal is accepted for handling by the processor.

Directed interrupt virtualization with fallback

An interrupt signal is provided to a first guest operating system. A bus attachment device receives an interrupt signal from a bus connected module with an interrupt target ID identifying a processor assigned for use by the guest operating system as a target processor for handling the interrupt signal. The bus attachment device checks whether the target processor is scheduled for usage by the guest operating system. If the target processor is not scheduled for usage, the bus attachment device forwards the interrupt signal using broadcasting and updates a forwarding vector entry stored in a memory section assigned to a second guest operating system hosting the first guest operating system. The update is used for indicating to the first operating system that there is a first interrupt signal addressed to the interrupt target ID to be handled.

Directed interrupt for multilevel virtualization

An input/output store instruction is handled. A data processing system includes a system nest communicatively coupled to at least one input/output bus by an input/output bus controller. The data processing system further includes at least a data processing unit including a core, system firmware and an asynchronous core-nest interface. The data processing unit is communicatively coupled to the system nest via an aggregation buffer. The system nest is configured to asynchronously load from and/or store data to an external device which is communicatively coupled to the input/output bus. The data processing unit is configured to complete the input/output store instruction before an execution of the input/output store instruction in the system nest is completed.

Handling an input/output store instruction

An interrupt signal is provided to a guest operating system. A bus connected module is operationally connected with a plurality of processors via a bus attachment device. The bus attachment device receives an interrupt signal from the bus connected module with an interrupt target ID identifying one of the processors assigned for use by the guest operating system as a target processor for handling the interrupt signal. The bus attachment device checks whether the target processor is running using a running indicator provided by an interrupt table entry stored in a memory operationally connected with the bus attachment device. If the target processor is running, the bus attachment device forwards the interrupt signal to the target processor for handling. A translation of the interrupt target ID to a logical processor ID of the target processor is used to address the target processor directly.

Directed interrupt virtualization with running indicator

An interrupt signal is provided to a first guest operating system. A bus attachment device receives an interrupt signal from a bus connected module with an interrupt target ID identifying a processor assigned for use by the guest operating system as a target processor for handling the interrupt signal. The bus attachment device translates the received interrupt target ID to a logical processor ID of the target processor using an interrupt table entry stored in a memory section assigned to a second guest operating system hosting the first operating system and forwards the interrupt signal to the target processor for handling. The logical processor ID of the target processor is used to address the target processor directly.

Directed interrupt for multilevel virtualization with interrupt table

An interrupt signal is provided to an operating system executed using one or more processors of a plurality of processors. A bus attachment device receives an interrupt signal with an interrupt target ID identifying a processor assigned for use as a target processor for handling the interrupt signal. The bus attachment device translates the received interrupt target ID to a processor ID using an interrupt table entry and forwards the interrupt signal to the target processor for handling. The processor ID is used to address the target processor directly.

Directed interrupt virtualization with interrupt table

An input/output store instruction is handled. A data processing system includes a system nest coupled to at least one input/output bus by an input/output bus controller. The data processing system further includes at least a data processing unit including a core, system firmware and an asynchronous core-nest interface. The data processing unit is coupled to the system nest via an aggregation buffer. The system nest is configured to asynchronously load from and/or store data to at least one external device which is coupled to the at least one input/output bus. The data processing unit is configured to complete the input/output store instruction before an execution of the input/output store instruction in the system nest is completed. The asynchronous core-nest interface includes an input/output status array with multiple input/output status buffers. The system firmware includes a retry buffer and the core includes an analysis and retry logic.

An input/output store instruction is handled. A data processing system includes a system nest coupled to at least one input/output bus by an input/output bus controller. The data processing system further includes at least a data processing unit including a core, system firmware and an asynchronous core-nest interface. The data processing unit is coupled to the system nest via an aggregation buffer. The system nest is configured to asynchronously load from and/or store data to at least one external device which is coupled to the at least one input/output bus. The data processing unit is configured to complete the input/output store instruction before an execution of the input/output store instruction in the system nest is completed. The asynchronous core-nest interface includes an input/output status array with multiple input/output status buffers.

A computing system includes an application configured to request execution of at least one translation including at least one command. A first coupling facility is configured to perform a first modification process to modify a first structure based on a received command associated with an ongoing transaction. A second coupling facility includes a secondary circular queue loaded with first data blocks indicating the first modification process, and is configured to output a message response block (MRB). The application determines a most recent modification process performed by the secondary coupling facility based on the MRB.

Computing system including enhanced application performance based on last completed operation sequence value

An interrupt signal is provided to a target processor. An interrupt signal is received with an interrupt target ID identifying a processor as a target processor for handling the interrupt signal. The interrupt signal is forwarded to the target processor for handling. A translation of the interrupt target ID to a logical processor ID of the target processor is used to address the target processor directly. The bus attachment device updates a directed interrupt signal indicator of a directed interrupt signal vector assigned to the target processor in order to indicate that there is an interrupt signal addressed to the respective interrupt target ID to be handled.

Interrupt signaling for directed interrupt virtualization

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Peter Dana Driever