Reshape, Inc.

Google Inc.

Magma Design Automation, Inc.

Hewlett-packard Development Company, L.p.

Silicon Graphics, Incorporated

Peter Dahl

Paul Kingsley Rodman

Byron Dickinson

Margie Levine

Robert Cypher

Steven Robert Schirripa

Sun C Chan

Shin-Ming Liu

Raymond W Lo

Frederick Chow

Mark Streich

Peng Tu

Robert Kennedy

Robert C Kunz

Jagat B Patel

Mike Coffin

Cheng-yeh Yen

A method includes identifying high-availability jobs and low-availability jobs that demand usage of resources of a distributed system. The method includes determining a first quota of the resources available to low-availability jobs as a quantity of the resources available during normal operations, and determining a second quota of the resources available to high-availability jobs as a quantity of the resources available during normal operations minus a quantity of the resources lost due to a tolerated event. The method includes executing the jobs on the distributed system and constraining a total usage of the resources by both the high-availability jobs and the low-availability jobs to the quantity of the resources available during normal operations.

Efficient resource utilization in data centers

An instance of a flow definition language for designing an integrated circuit implementation flow. The instance of the flow definition language includes a hierarchical collection of stages for a physical chip design. Relational constraints define the execution order of a plurality of tasks in the hierarchical collection of stages. Parameters customize the plurality of tasks. The relational constraints and parameters are hierarchically defined, such that higher order definitions in the hierarchical collection of stages override lower level definitions of the relational constraints and parameterized knobs.

Flow definition language for designing integrated circuit implementation flows

Methods for generating a padring layout design are described. These methods utilize automation while still allowing customization. Automation is emphasized as much as possible so that more time can be used to solve the various problems that make each padring layout design unique. A framework in which regular patterns can be described, replicated, and tailored is provided. The padring is broken down into zones in which slots having bumps/bond pads areas, I/O cell areas, and/or edge logic cell areas are laid out in a regular pattern through an instantiation process. Edge logic, which is comprised of standard cells, is pulled from the core of the chip because these cells couple directly to I/O cells and are critical for timing. The framework allows the bumps/bond pads, I/O cells, and edge logic cells to be laid out in respective bumps/bond pads areas, I/O cell areas, and/or edge logic cell areas according to algorithms associated with the patterns and using a variety of maps which associate the logical netlist with the physical layout design.

Method of optimizing placement and routing of edge logic in padring layout design

An abutted-pin hierarchical physical design process is described. The abutted-pin hierarchical physical design provides solutions to the problems of the traditional hierarchical physical design and provides additional advantages and benefits. In particular, the abutted-pin hierarchical physical design does not have channels. Moreover, in the abutted-pin hierarchical physical design, components of the top-level are merged into the block-level so that the top-level netlist is reduced significantly.

Optimization of the top level in abutted-pin hierarchical physical design

Optimization of abutted-pin hierarchical physical design

Facilitating press operation in abutted-pin hierarchical physical design

Method of generating the padring layout design using automation

Facilitating verification in abutted-pin hierarchical physical design

Method of customizing and using maps in generating the padring layout design

The present invention is a method and apparatus for compiler optimization that determines the maximum number of live computer registers, or pressure point. The present invention improves the productivity of a software developer by reducing compilation time of a computer program. More particularly, the overhead required during compilation to search information to determine the maximum number of live registers is reduced. The present invention records the relevant events related to the execution of a computer program, as opposed to a comprehensive history of the read instructions and write instructions. Also, the present invention maintains information about the maximum number of live registers for any partition related to the execution of a computer program. The present invention may bound the required system resources required to determine the maximum number of live registers to the number of registers associated with the number of partitions.

Determining maximum number of live registers by recording relevant events of the execution of a computer program

A method and system for automatically generating low level design tool commands as dependency graphs from abstracted high level physical design stages. The novel system inputs names of blocks of a hierarchical integrated circuit. Each block name has associated with it certain variables, stages and conditional statements. The stages represent a set of linked physical design processes that are to be executed on the block. Stages can be dependent on other stages and therefore are executed in-order on the block depending on how they are linked in the input set. The system automatically generates, from the input set, a dependency graph for each block. The dependency graph includes a large volume of nodes with associated parameters and options. Each node includes one or more low level program commands (&ldquo;tasks&rdquo;) for directing a number of physical design tools, e.g., programs, to perform various functions with respect to the block. Each node can receive input and generate an output. If the input to a particular node has not been altered, e.g., since the last time the graphs were executed, then that node is not executed in the current run. Dependency graphs that are not data dependent can be executed in parallel. If the input set is altered, a new set of dependency graphs can automatically be generated. By grouping the physical design operations into stages, the novel system allows the user to abstract the problem of dealing with large numbers of physical design tasks into the more manageable problem of dealing with high level &ldquo;stages&rdquo; in the physical design process.

Method and system for automatically generating low level program commands as dependency graphs from high level physical design stages

A method for implementing a user interface for performing physical design operations on an integrated circuit netlist. The method includes accessing an input file containing identifications of a plurality of blocks of cells of the integrated circuit netlist, each block representing circuit components to be realized in physical form. A view of the plurality blocks is presented to a user, the view provided by a computer display. Attach points are defined for each block. Connections for the blocks are defined by graphically linking the attach points of the respective blocks. The input file is updated in accordance with the defined connections.

Method and system for implementing a graphical user interface for defining and linking multiple attach points for multiple blocks of an integrated circuit netlist

A method for implementing a user interface for performing physical design operations on an integrated circuit netlist. The method includes accessing an input file and parsing the input file to identify elements within the netlist matching corresponding elements within a first library file. At least one element within the netlist is identified that does not have a corresponding element within the first library file. A modifiable element corresponding to the at least one element is stored within a second library file. A subsequent occurrence of the at least one element is matched to the modifiable element in the second library file. The parsing of the input file of the integrated circuit netlist is completed and a build of the integrated circuit netlist is then completed based on the parsed input file and specifications stored in the first or second library files.

Method and system for maintaining element abstracts of an integrated circuit netlist using a master library file and modifiable master library file

A method for implementing a user interface for performing physical design operations on an integrated circuit netlist. The method includes accessing vertical and horizontal dimensions of an area of an integrated circuit netlist and accessing a grid for power and ground lines of the integrated circuit netlist. A view is presented of the grid to a user by a computer display. A plurality of blocks of cells of the integrated circuit netlist are accessed, wherein each block represents circuit components to be realized in physical form. The dimensions of the plurality of blocks to the grid such that the dimensions of the blocks align with the grid.

Method and system for implementing a user interface for performing physical design operations on an integrated circuit netlist

Growing community of inventors

Cupertino, CA, United States of America

Peter Dahl