Sony Electronics Inc

Sony Corporation of Japan

3dfx Interactive, Inc.

Peter D Robertson

Andrew J Tao

A content addressable memory with an internally-timed write operation includes a data input for receiving a input word. Coupled to the data input are a plurality of storage registers comprising stored words. Each storage register includes a comparison circuit for comparing the stored word with the input word and producing therefrom a match output indicating a match when the stored word matches the input word, and indicating a miss when the stored word does not match the input word. Coupled to the storage registers is a miss detector for generating a miss signal responsive to each of the match outputs of the storage registers indicating a miss. Coupled to the miss detector is a write cycle circuit for writing the input word to at least one of the storage registers responsive to receiving the miss signal.

Content addressable memory with an internally-timed write operation

The present invention relates to methods and apparatus for mapping spare columns to defective columns in a fabricated random access memory (RAM). The defective columns correspond to improperly fabricated bit lines in the RAM and spare columns are fabricated on the RAM to replace any defective columns. Particular arrays of columns in the RAM are accessed through a corresponding input/output device. A defective column in an array is bypassed by a column redundancy scheme that allows a spare column to be mapped to more than one array of columns. Thus, a plurality of spare columns may be mapped to each array of columns. Since the total number of spare columns may be less than the total number of column arrays, the present invention provides a saving over the prior art which requires one spare column for each column array.

Column redundancy scheme for a random access memory incorporating

A bit line conditioning circuit for a random access memory (RAM) is provided. A pair of driver transistors maintain the bit line and bit line inverse at a high voltage before a memory cell is accessed. When a memory cell is accessed, the driver transistors are turned off such that the memory cell is accessed when the bit line and bit line inverse are not statically loaded. Since the bit line and bit line inverse are not statically loaded when the access is initiated, a read or write operation occurs more quickly than in a prior art RAM. An equalization transistor is coupled across the bit line and bit line inverse, and is turned on when a memory access is initiated to equalize the value over the bit line and bit line inverse.

Growing community of inventors

Fremont, CA, United States of America

Peter D Robertson