Intel Corporation

Other

Rambus Inc.

Peter D MacWilliams

Stephen S Pawlowski

William S Wu

Nitin V Sarangdhar

James E Akiyama

Gurbir Singh

Douglas L Gabel

Konrad K Lai

Randy M Bonella

Bindi A Prasad

Gary A Solomon

Robert L Farrell

Thomas J Holman

Nicholas D Wade

Norman J Rasmussen

Kuljit Singh Bains

Michael W Rhodehamel

George R Hayek

Muthurajan Jayakumar

Dilip K Sampath

Frederick Abbott Ware

Craig Edward Hampel

Richard Maurice Barth

Donald C Stark

Andrew V Anderson

Brian K Langendorf

Abhijit Mukun Abhyankar

James M Dodd

Bryce D Horine

Matthew A Fisch

Michael W Leddige

Aniruddha Kundu

Clair C Webb

Ely K Tsern

Edward Thomas Grochowski

David Nguyen

Sridhar Lakshmanamurthy

Paul G Davis

Harry Muljono

James A Gasbarro

Howard S David

Amit A Merchant

Duane G Quiet

D Michael Bell

Narjala Prakash Bhasker

Thomas J Mozdzen

Dan Wheeler Patterson

Sunny C Huang

Dror Avni

Len J Schultz

Sean T Murphy

Adalberto Golbert

Jerzy B Kolinski

Abid Asghar

Phil G Lee

Manoji Khare

Steve Hunt

Itzik Silas

David M Cowan

Anan Baransy

Avi Liebermensch

Stephen J Packer

In one embodiment of the invention, a memory integrated circuit is provided including an address decoder to selectively access memory cells within a memory array; a mode register with bit storage circuits to store an enable bit and at least one sub-channel select bit; and control logic. The control logic is coupled to a plurality of address signal lines, the address decoder, and the mode register. In response to the enable bit and the at least one sub-channel select bit, the control logic selects one or more of the address signal lines to capture independent address information to support independent sub-channel memory accesses into the memory array. The control logic couples the independent address information into the address decoder.

Memory controller interface for micro-tiled memory access

In one embodiment of the invention, a memory integrated circuit is provided including a memory array, a register, and control logic coupled to the register. The memory array in the memory integrated circuit stores data. The register includes one or more bit storage circuits to store one or more identity bits of an identity value. The control logic provides independent sub-channel memory access into the memory integrated circuit in response to the one or more identity bits stored in the register.

Identifying and accessing individual memory devices in a memory channel

Micro-tile memory interfaces

A bus agent defers an ordered transaction if the transaction cannot be completed in order. When an ordered transaction is deferred, its visibility for the next ordered transaction is asserted if it can guarantee a sequential order of the ordered transaction and the next ordered transaction. This visibility indication allows the bus agent to proceed with the next ordered transaction without waiting for the completion status of the deferred transaction. The visibility indication provides fast processing of ordered transactions.

Mechanism for efficiently processing deferred order-dependent memory access transactions in a pipelined system

A memory system comprising an expansion buffer and a memory expansion channel for connecting a large array of memory devices, such as Direct RDRAMs, to a memory controller. The memory devices are partitioned into subsets of memory devices so that each subset is connected to a unique memory channel for sending and receiving data. The expansion buffer and memory expansion channel provide communication with the memory devices via control packets on the expansion bus, where each control packet has a channel identification field to store a channel identifier; and via request packets on the expansion bus, where each request packet is associated with a control packet. The expansion buffer routes a request packet to a unique channel based upon the channel identifier stored in the associated control packet.

Memory expansion channel for propagation of control and request packets

A method and apparatus for transferring data between bus agents in a computer system. The present invention includes transmitting a control signal, from a first agent to a second agent, via a first transfer protocol; and, transmitting data corresponding to the control signal, from the first agent to the second agent, via a second transfer protocol. In one embodiment, the control signals are transmitted from the first agent to the second agent via a synchronous transmission with respect to a bus clock; and, the data is transmitted via an asynchronous transmission with respect to the bus clock, which has a data width greater than the synchronous transmission. In addition, in one embodiment of the present invention, the synchronous transmission is a common clock data transfer protocol, and the asynchronous transmission is a source clock data transfer protocol.

Transmission of signals synchronous to a common clock and transmission of data synchronous to strobes in a multiple agent processing system

A computer system memory module includes a bi-directional repeater hub that in a first direction takes as an input a memory bus signal in a first port, regenerates the memory signals, and outputs the regenerated memory signal at a second port as at least one separate signal for coupling to a memory bus for each of the regenerated separate signals. In a second direction, the bi-directional repeater hub takes as input at least one memory bus signal at the second port, regenerates each input memory bus signal, and outputs the regenerated memory signal at the first port for coupling to a memory bus.

Method and apparatus for implementing multiple memory buses on a memory module

A method and apparatus for detecting errors in data output from memory and a device failure in the memory. In the invention, a check code is generated based on data to be input to the memory. The check code is valid when equal to zero. The check code is inverted and input along with the data as a codeword to the memory in response to a write command. The codeword is output from the memory in response to a read command. The codeword output from memory indicates whether a device in memory has failed. The inverted check code included in the codeword output from memory is re-inverted. Information indicating whether the data included in the codeword output from memory includes an error is generated based on the data and the codeword including the check code.

Method and apparatus for detecting errors in data output from memory and a device failure in the memory

A computer system memory module includes a bi-directional repeater hub that in a first direction takes as an input a memory bus signal in a first port, regenerates the memory signals, and outputs the regenerated memory signal at a second port as at least one separate signal for coupling to a memory bus for each of the regenerated separate signals. In a second direction, the bi-directional repeater hub takes as input at least one memory bus signal at the second port, regenerates each input memory bus signal, and outputs the regenerated memory signal at the first port for coupling to a memory bus. A method includes determining whether a memory device to which signals are addressed is on a first memory module. Signals are routed to a first memory bus on the first memory module connected to the memory device if the memory is on the first memory module. Signals are routed to a second memory bus on a second memory module if the memory device is not on the first memory module.

Method for implementing multiple memory buses on a memory module

A computer system is disclosed with a host bridge that arbitrates access to a system resource from a CPU via a host bus and from a set of bus agents via a peripheral bus. A separate set of priority classes are provided to the CPU and to the bus agents and programmable timers are included to tune system resource allocation between the host and processor busses.

System resource arbitration mechanism for a host bridge

A method and apparatus for supporting multiple overlapping address spaces on a shared bus includes both an address comparator and an address size indicator. The address comparator compares an address, corresponding to a request to be issued on the bus, to a plurality of address spaces. The address size indicator indicates a first address space of the plurality of address spaces to which the address corresponds.

Method and apparatus for supporting multiple overlapping address spaces on a shared bus

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Aloha, OR, United States of America

Peter D MacWilliams