Globespan, Inc.

Ikanos Communications, Inc.

Globespan Virata Corporation

Peter D Keller

Nianxiong Tan

Sigurd Schelstraete

Massimo Sorbara

Arnold Muralt

Daniel Amrany

Frode Larsen

John M Ross

Robert A Day

Jung-Lung Lin

Sam Olu George

Min Shen

Systems and methods for synchronizing a clock at a customer premises equipment (CPE) location with a master clock at a central office (CO) location are described. One embodiment is a method that comprises receiving, by a time-of-day transmission convergence (ToD-TC) module in the CPE, ToD information relating to the master clock. Based on the received information, time stamps are applied to reference data samples. The method further comprises transporting the ToD information by transporting the reference data samples with applied time stamps and utilizing time stamps of the reference data samples to synchronize the CPE clock with the master clock.

Systems and methods for transporting time-of-day information in a communication system

A system and method is presented for dividing a reference clock frequency by any real number. The invention allows for a real number divisor that could have any desired degree of precision. Additionally, the invention seeks to minimize hardware complexity in realizing such a reference-clock frequency divider. In one particular embodiment of the invention, a system and method is presented, wherein the real number divisor is a real number having a repeating decimal (i.e., the real number may be represented by a fraction).

Digital frequency divider

In general, the multi-mode analog front-end provides an internal line driver and hybrid, as well as numerous functions, in order to provide a close to optimum solution for all digital subscriber line applications. The functions provided for by the analog front-end include; programmable hybrid attenuation; onboard amplifiers for driving external transmit and receive filters; a line driver with programmable drive and gain; programmable RC-filters capable of calibration via an internal loop-back under digital control; a programmable switched-capacitor filter for tracking the over sampling rate used by a digital signal processor; internal testing functions; a high frequency boost circuit; a dual input peak detector; selectable data rates; and a programmable data interface. The analog front-end allows for use of particular blocks within the analog front-end particular to the functions necessary to compensate for a particular digital subscriber line application.

Multi-mode analog front-end

The disclosure is generally directed to an improved structure for a decimation filter. More specifically, the disclosure includes a method and apparatus for decimating an oversampled signal at the input, which is the output of an oversampling analog-to-digital converter. In accordance with one aspect of the system, an apparatus is provided for decimating an oversampled signal. The apparatus includes at least one non-recursive decimator. Specifically, the at least one non-recursive decimator is configured to receive the oversampled input signal defined by a first sampling frequency. This at least one non-recursive decimator is further configured to generate a output having a second sampling frequency. The apparatus further includes a recursive decimator. The recursive decimator is configured to receive the output of the at least one non-recursive decimator and generate an output having third sampling frequency. It will be appreciated that the second sampling frequency output from the non-recursive decimator is less than the sampling frequency of the oversampled input signal, and further that the third sampling frequency is less that the second sampling frequency. In accordance with another aspect of the disclosure, a method is provided for decimating an oversampled signal. Broadly, the method includes the steps of decimating the oversampled signal in accordance with a non-recursive decimation algorithm to generate an interim decimated signal, and decimating the interim decimated signal in accordance with a recursive decimation algorithm to generate a final decimated signal.

Decimation filter for oversampling analog-to digital converter

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Tinton Falls, NJ, United States of America

Peter D Keller