International Business Machines Corporation

Other

Kabushiki Kaisha Toshiba

Infineon Technologies Ag

Siemens Components, Inc.

Peter D Hoh

Jeffrey P Gambino

Richard Anthony Conti

Michael D Armacost

Richard Stephan Wise

Ramachandra Divakaruni

Son Van Nguyen

Laertis Economikos

Gary Bela Bronner

Chandrasekhar Narayan

David M Dobuzinsky

Mary Elizabeth Weybright

Christoph S Harder

Uwe Schroeder

Kenneth C Arndt

Greg Costrini

Wendy Yan

Arsam Antreasyan

David V Horak

Peter Vettiger

Tokuhisa Ohiwa

Gregory Costrini

Mark A Jaso

Kurt R Grebe

Peter L Buchmann

Ernest N Levine

David J Webb

Waldemar Walter Kocon

Thomas S Rupp

Virinder Grewal

Bruno Spuler

Wilhelm Heuberger

Volker Graf

Senthil Srinivasan

Myra N Boenke

Guadalupe Wiltshire

Theodor O Mohr

A method of etching an organic antireflective film layer underlying a patterned resist layer on a semiconductor substrate by contacting the exposed organic film with a fluorocarbon and nitrogen etchant in the presence of a plasma-generated energy and removing exposed areas of the organic film with the etchant. An oxide layer underlying the organic film layer is substantially undamaged after contact with the etchant. The plasma is a high density plasma and preferably contains argon, C F , and nitrogen.

Nitrogen-based highly polymerizing plasma process for etching of organic materials in semiconductor manufacturing

Two different gate conductor dielectric caps are used in the array and support device regions so that the bitline contact can be fabricated in the array region, but a thinner hard mask can be used for better linewidth control in the support device region. The thinner dielectric cap is made into dielectric spacers in the array device regions during support mask etching. These dielectric spacers allow for the array gate conductor resist line to be made smaller than the final gate conductor linewidth. This widens the array gate conductor processing window. The second dielectric cap layer improves linewidth control for the support devices and the array devices. Two separate gate conductor lithography steps and gate conductor dielectric etches are carried out in the present invention to optimize the gate conductor linewidth control in the array and support device regions. The gate conductors in the array and support devices regions are etched simultaneously to reduce production cost. In additional embodiments of the invention, dual workfunction support device transistors with or without salicide can be fabricated with an array including borderless contacts.

Modified gate processing for optimized definition of array and logic devices on same chip

A silicon article including a silicon base and columns extending from the silicon base. The columns define a gap between the columns which is devoid of material so that the article can act as a filter or heat sink. Also disclosed is a method of making the silicon article.

Method of making silicon article having columns

In one aspect, the present invention discloses a transistor device (see e.g., FIG. ) that includes first and second source/drain regions and disposed in a semiconductor body and separated by a channel region A dielectric layer overlies the channel region and a gate electrode overlies the dielectric layer In the preferred embodiment, the gate electrode includes a polysilicon layer that extends a first lateral distance over the dielectric layer and a silicide layer that extends a second lateral distance over the first polysilicon layer. In this example, the first lateral distance is greater than the second lateral distance.

Semiconductor contact and method of forming the same

Two different gate conductor dielectric caps are used in the array and support device regions so that the bitline contact can be fabricated in the array region, but a thinner hard mask can be used for better linewidth control in the support device region. The thinner dielectric cap is made into dielectric spacers in the array device regions during support mask etching. These dielectric spacers allow for the array gate conductor resist line to be made-smaller than the final gate conductor linewidth. This widens the array gate conductor processing window. The second dielectric cap layer improves linewidth control for the support devices and the array devices. Two separate gate conductor lithography steps and gate conductor dielectric etches are carried out in the present invention to optimize the gate conductor linewidth control in the array and support device regions. The gate conductors in the array and support devices regions are etched simultaneously to reduce production cost. In additional embodiments of the invention, dual workfunction support device transistors with or without salicide can be fabricated with an array including borderless contacts.

An integrated circuit and method of making the integrated circuit. Air gaps are formed between surfaces of current-conducting lines that face one another and dielectric material disposed between these surfaces of the current-conducting lines. A liner material is applied to these surfaces of the current-conducting lines and, after the dielectric material is introduced between the current-conducting lines, the liner material is removed, for example by etching, leaving air gaps between the current-conducting lines and the dielectric material. These air gaps eliminate or greatly reduce the effect of capacitive currents across the dielectric material between the current-conducting lines.

Integrated circuit having air gaps between dielectric and conducting lines

By providing a photoresist material with a protective polymer layer during the etching of an organic anti-reflective coating, undue damage to the photoresist material can be avoided during opening of the anti-reflective coating without the need for an oxidant. The preferred polymer chemistry system for producing such a result includes a fluorohydrocarbon-containing polymer mixture with a strong source of CF,, preferably C,F,. The etchant also includes a source of hydrogen selected from CH,F, C,HF,, or CH,F,, and a diluent selected from Ar, He or N,.

High-density plasma, organic anti-reflective coating etch system compatible with sensitive photoresist materials

The stresses commonly induced in the dielectrics of integrated circuits manufactured using metal patterning methods, such as reactive ion etching (RIE) and damascene techniques, can be reduced by rounding the lower corners associated with the features which are formed as part of the integrated circuit (e.g., the interconnects) before applying the outer (i.e., passivation) layer. In connection with the formation of metal lines patterned by a metal RIE process, such corner rounding can be achieved using a two-step metal etching process including a first step which produces a vertical sidewall and a second step which tapers lower portions of the vertical sidewall or which produces a tapered spacer along the lower portions of the vertical sidewall. This results in a rounded bottom corner which improves the step coverage of the overlying dielectric, in turn eliminating the potential for cracks. For metal lines patterned by damascene, such corner rounding can be achieved using a two-step trench etching process including a first step which produces a vertical sidewall, and a second step which produces a tapered sidewall along lower portions of the vertical sidewall.

Integrated circuits having reduced stress in metallization

Silicon article having columns and method of making

A method for depositing materials on a surface, having the following steps: a) obtaining a surface having at least feature thereon, the surface and the feature having a layer of first material deposited thereon, the first material not filling substantially all of the feature; b) depositing a layer of a second material on the first material, wherein the melting point of the second material is less than that of the first material, and wherein the first material is soluble in the second material at a temperature less than the melting point of the first material; and c) heating the surface to a first temperature of at least equal to the melting point of the second material and at most equal to the melting point of the first material, wherein substantially all of the via is filled with the first material.

Low temperature via fill using liquid phase transport

Method for reducing stress in the metallization of an integrated circuit

Metal silicide is removed at a faster rate than polysilicon in dry etching of metal silicide/polysilicon composites with an etching gas made from HCl and Cl.sub.2 at a volumetric flowrate ratio of HCl:Cl.sub.2 within the range of 3:1 to 5:1.

Polycide etching with HCL and chlorine

The present invention provides an improved semiconductor ridge waveguide laser structure having a plurality of layers including an N-InP buffer layer and an N-type InP substrate, a thin InGaAsP active layer 1100 Angstroms thickness, a P-InP graded layer, an optional etch stop layer, a P-InP cladding layer and a P+InGaAs. The ridge waveguide laser of the present invention demonstrates a very high reliability and the fabrication process therefor is high yield. The ridge waveguide laser of the present invention demonstrates very good high temperature behavior and the design suppresses higher order modes.

Ridge waveguide semiconductor laser with thin active region

A protection configuration for a semiconductor ridge waveguide laser structure is disclosed wherein layers of protective metal in the form of walls, is applied on each side of the ridge element of the ridged layer of the laser structure. The laser structure is then bonded to a mounting plate in a junction side down orientation by solder or a junction side up orientation by wire bonding. The metal layer may be composed of gold.

Waveguide ridge laser device with improved mounting and ridge protection

A process for forming the ridge structure of a self-aligned InP-system, double heterostructure (DH) laser, particularly useful for long wavelength devices as required for signal transmission systems includes a thin Si.sub.3 N.sub.4 layer (41) inserted between a photoresist mask (42) that defines the ridge structure, and a contact layer (35). Using a Si.sub.3 N.sub.4 layer (4) deposited at a high plasma excitation frequency (RF) for adhesion promotion, and a low frequency deposited (LF) Si.sub.3 N.sub.4 layer (43) for device embedding, provides for the etch selectively required in the process step that is used to expose the contact layer to ohmic contact metallization deposition.

Process for forming the ridge structure of a self-aligned semiconductor

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Hopewell Junction, NY, United States of America

Peter D Hoh