Bell Telephone Laboratories

Itt Corporation

Itt Manufacturing Enterprises, Inc.

Peter Cummiskey

Marvin A Epstein

Richard Kim

Paul A Gilmour

Lawrence J Doyle

Dennis D McCrady

Leslie A Baxter

Howard Scott Forstrom

Bryan S Majkrzak

A position location communication system determines the position of a mobile master radio using a round-trip messaging scheme in which the time of arrive (TOA) of ranging signals is accurately determined to yield the range estimates required to calculate the position of the mobile radio. The master radio transmits ranging signals to plural reference radios which respond by transmitting reply ranging signals. Upon reception of the reply ranging signal, the master radio determines the range to the reference radio from the signal propagation time. Any combination of fixed or mobile radios having known positions can be used as the reference radios for another mobile radio in the system. Individual radios do not need to be synchronized to a common time reference, thereby eliminating the need for highly accurate system clocks. Errors in TOA estimates are minimized by performing internal delay calibration, Doppler compensation, leading-edge-of-the-signal curve fitting and frequency diversity techniques.

Method and apparatus for determining the position of a mobile communication device

A system and method for maintaining a precise time standard among a system of orbiting satellites is disclosed. In an illustrative embodiment, atomic clock data is circulated among the satellites via RF crosslinks. Each satellite uses the received data as input to a Kalman process which acts to minimize the mean squared error among the satellite clocks to form a set of 'ensemble clocks'. The resulting ensemble clock values are then transmitted to an earth station where an offset between the ensemble clocks and Universal Time is computed. The offset is transmitted from the earth station to the satellites where it is used by the satellites to lock their on-board clocks to Universal Time, thereby creating a corrected system time. The corrected system time is transmitted, via RF crosslinks, to satellites not having operational on-board clocks. The satellites without atomic clocks employ phase locked loops to anchor their clocks to the corrected system time as it is received over the crosslinks.

RF link control of satellite clocks

An echo cancellation apparatus is included in a variable rate modem. The echo cancellation apparatus includes a local echo canceler, a remote echo canceler and a quadrature echo canceler unit. The local and remote echo cancelers both operate to cancel echoes in a similar manner employing topped delay lines or transversal filters wherein the taps of each delay line are adjusted to accommodate both local and remote echo cancellation. The local echo canceler and the remote echo canceler share many programs in common. However, the remote echo canceler operates with a phase lock loop which essentially derives a signal obtained from the quadrature and local echo cancelers which signal is further correlated with the output residuals from the local echo canceler to develop samples applied to the remote echo canceler and to derive a frequency which is indicative of a offset carrier frequency to enable the remote echo canceler to cancel remote echoes. Remote echoes are due to frequency shifts occurring remote from the modem, such as those caused by changes in satellite positions or changes in frequency sources. The remote echo canceler operates to cancel echoes which are greater than 15 milliseconds in delay, as compared to local echoes, which are canceled by the local echo canceler responding to echoes which are delayed 15 milliseconds or less.

Local and remote echo canceling apparatus particularly adapted for use

Multirate wire line modem apparatus operable at either of two rates in either transmission or reception modes is provided according to the teachings of the instant invention. Full duplex operation and echo cancellation are utilized for both voice and data. Structurally an IOP processor acts as a system controller in controlling transmission and reception digital signal processors which provide the independent transmission and reception functions of the resulting multirate modem apparatus.

Multirate wire line modem apparatus

A data communication arrangement is disclosed for multiplexing an asynchronous binary data signal with a synchronous binary data signal by the timely insertion of an extra data bit in selected synchronous data words and by delaying the transmission of the resulting multiplexed data words. The extra data bit is generated when a binary level transition occurs in the asynchronous binary data signal. The transmission of the multiplexed data word is delayed a fixed amount of time relative to the binary level transition of the asynchronous signal to preserve the timing between transitions in the asynchronous signal. The received multiplexed data words are demultiplexed into a synchronous and asynchronous binary data signals. The demultiplexed asynchronous binary data signal emerges having transition timing which is the same as the transition timing of the original asynchronous binary data signal.

Synchronous/asynchronous data communication arrangement

A frame synchronization arrangement is disclosed for use in a digital data transmission system which utilizes a redundant data word transmission. A selected data word of each frame of data having a fixed location relative to the frame boundary is transmitted twice to provide a framing signal for the receiver circuit. At the receiver circuit the data is shifted through a shift register where a comparator checks predetermined locations of the shift register for redundant data words in the received data stream. Once the redundant data words are detected a valid word received signal is generated. The existence of the valid word received signal together with the known relationship between the location of the redundant word and the frame boundary is used to provide a framing signal.

Redundant word frame synchronization circuit

There is disclosed a digital loop circuit for controlling synchronization around a closed loop communication system. The control circuit is designed to automatically adjust the delay of the loop to maintain a constant frame bit length without regard to the number of stations connected into the loop. As stations are added or subtracted from the loop, the system operates to add or subtract delay as necessary. A FIFO register having a bit capacity equal to the frame size is inserted serially in the loop and a separate clock is used to control the input and the output of the FIFO register. If a unique frame bit is not received in the anticipated position the output FIFO clock skips one count per frame thereby adding delay to the loop. The loop control circuit operates for situations where the framing bit is on a separate channel and also when the framing bit is on the actual data channel.

Digital loop synchronization circuit

The disclosed full duplex bit synchronous data rate buffer (15) adapts high speed burst data signals for transmission over low speed data facilities. The data rate buffer (15) includes a buffer control circuit (201-205, 105) for interactively controlling a first data buffer (101) for down-converting the high speed signals (107) to low speed signals (109) and a second data buffer (102) for up-converting low speed data signals (108) to high speed burst data signals (106). The data rate buffer (15) accepts random changes in the length of each high speed burst data signal without a loss in bit synchronism and adjusts for changes in the number of burst data signals contained in each frame.

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Clark, NJ, United States of America

Peter Cummiskey