Texas Instruments Corporation

Sgs-thomson Microelectronics Limited

Sgs-thomas Microelectronics Pte. Ltd.

Peter Cumming

Richard Grisenthwaite

Franck Benjamin Dahan

Alain Bruno Chateau

Christian Roussel

Donald Edward Steiss

Clive D Bittlestone

Christopher Barr

A digital system is provided with a secure mode (3level of privilege) built in a non-invasive way on a processor system that includes a processor core, instruction and data caches, a write buffer and a memory management unit. A secure execution mode is thus provided on a platform where the only trusted software is the code stored in ROM. In particular the OS is not trusted, all native applications are not trusted. A secure execution mode is provided that allows virtual addressing when a memory management unit (MMU) is enabled. The secure execution mode allows instruction and data cache to be enabled. A secure execution mode is provided that allows all the system interruptions to be unmasked. The secure mode is entered through a unique entry point. The secure execution mode can be dynamically entered and exited with full hardware assessment of the entry/exit conditions. A specific set of entry conditions is monitored that account for caches, write buffer and MMU being enabled. The structure of the activation sequence code accounts for caches, write buffer and MMU being enabled. The structure of the exit sequences code accounts for caches, write buffer and MMU being enabled. A specific way is provided to manage a safe exit of secure mode under generic interruptions and allows return from interruption through entry point and activation sequence and a proper resuming of the secure execution. A specific way is provided to manage the MMU in secure mode and provide data exchange between secure and non-secure environment.

Secure mode for processors supporting MMU and interrupts

Secure mode for processors supporting interrupts

Secure mode for processors supporting MMU

A flip flop ( ) comprising a master stage ( ) comprising a first plurality of transistors ( ), wherein each of the first plurality of transistors comprises a selective conductive path between a source and drain. The flip flop also comprises a slave stage ( ) comprising a second plurality of transistors ( ), wherein each of the second plurality of transistors comprises a selective conductive path between a source and drain. For the flip flop, in a low power mode the flip flop is operable to receive a first voltage (V ) coupled to the selective conductive path for each of the first plurality of transistors. Also in the low power mode, the flip flop is operable to receive a second voltage (V ) coupled to the selective conductive path for each of the second plurality of transistors. Lastly, the second voltage is greater than the first voltage in the low power mode.

Flip flop with reduced leakage current

A computer instruction supply system has store and fetch circuitry for obtaining a sequence of instructions, test circuitry for locating the first instruction in the sequence to be enabled, and for testing separately successive instructions in the sequence to locate any branch instruction which is predicted to be taken and control circuitry to disregard target addresses of branch instructions in the sequence prior to the first instruction to be executed.

Computer instruction supply

A cache memory comprises a CAM and a data RAM, the CAM has an associate input and a write input, the associate input being connected to selection circuitry to select write data or associate data so that an associate operation can be effected in parallel with a write operation using the same data to control validation of the write input.

Avoidance of cache synonyms

A cache memory has a plurality of cache partitions each having a CAM array, a data RAM and output control circuitry which determines a different priority for each cache partition and permits a cache hit output only from one partition which has the highest priority with a cache hit.

Cache memory

A branch target buffer comprises a partitioned cache memory having for each partition a CAM array holding the least significant bits of a fetch address, a RAM holding the least significant bits of a target address, and comparators for comparing the most significant bits of the fetch and target addresses to control entry of a branch instruction into the buffer.

Growing community of inventors

La Gaude, France

Peter Cumming