International Business Machines Corporation

Peter Claude Elmendorf

Harry John Beatty, Iii

Kerim Kalafala

Chen Luo

Stephen Gerard Shuma

Charles Gates

Jeffrey G Hemmett

Alexander Joel Suess

Eric A Foreman

Michael H Wood

Debjit Sinha

Nathan C Buck

Jason David Morsey

Sean Michael Carey

Jeannie H Panner

Steven Eugene Washburn

Bijan Salimi

Chaitanya Ravindra Peddawad

Lansing Dunn Pickup

Lyle Jackson

Unmesh A Ballal

Prabhat Maurya

Qi Yan

The efficiency of electronic design automation is increased by building, as an electronic data structure, a timing graph characterizing a putative integrated circuit design; identifying at least one of an edge and a node in the timing graph that requires canonical timing adjustment; and electronically calculating a deterministic timing adjustment for each of a plurality of corner cases. Based on the calculated deterministic timing adjustment for each of the plurality of corner cases, the canonical timing adjustment is determined for the at least one of an edge and a node; the canonical timing adjustment is applied to the timing graph; and the timing graph is updated based on the application of the canonical timing adjustment.

Efficient projection based adjustment evaluation in static timing analysis of integrated circuits

A design and timing model for at least one circuit path of at least a portion of an IC design is loaded into a computer. At least one canonical clock variable associated with the model is defined; it includes at least one source of variation. The computer is used to perform an SSTA of the at least one circuit path, based on the design and timing model and the at least one canonical clock variable, to obtain slack canonical data. A clock period is projected, based on the slack canonical data, such that a cycle time canonical is projected to a different space than a logic canonical. Results of the SSTA and the projected clock period are output to determine performance compliance. Efficient operation of the computer is enhanced by analyzing a slack vector in a single timing run, loaded once, and multithreading timing propagation.

Independently projecting a canonical clock

A method, system, and computer program product to integrate functional analysis and common path pessimism removal (CPPR) in static timing analysis include determining initial path slack for a path for a given timing analysis test. The method also includes comparing the initial path slack with a threshold value to determine if the path passes or fails the given timing analysis test, and based on the path failing the given timing analysis test, performing the functional analysis on the path only based on performing the CPPR on the path, or performing the CPPR on the path only based on a result of performing the functional analysis on the path.

Integration of functional analysis and common path pessimism removal in static timing analysis

Aspects relate to a computer implemented method for timing analysis and pessimism removal of an integrated circuit. The computer implemented method includes performing, using a processor, a static timing analysis of the integrated circuit and generating timing data, generating a light weight path signature of a path using the generated timing data, performing common path pessimism removal (CPPR) using the light weight path signature and generating CPPR information, and storing, in a storage medium, the light weight path signature and the corresponding CPPR information. The method also includes generating a timing report using the light weight path signature and the corresponding CPPR information, wherein the timing report includes full path details generated using at least the light weight path signature, and reporting the timing report with full path details and corresponding CPPR information.

System and method for combined path tracing in static timing analysis

A method of delegating work of a computer program across a mixed computing environment is provided. The method includes: performing on one or more processors: allocating a container structure on a first context; delegating a new operation to a second context based on the container; receiving the results of the new operation; and storing the results in the container.

Methods and systems for delegating work objects across a mixed computer environment

A method of linking a computer program across a mixed computing environment is provided. The method includes, performing on one or more processors: identifying signatures of elements of the computer program; loading a plurality of modules of the computer program; and linking the plurality of modules using the signatures of the elements.

Methods and systems for linking objects across a mixed computer environment

A method of debugging a computer program across a mixed computing environment is provided. The method includes attaching a first debug module to a first program module of the computer program, where the first program module is operating on a first node; attaching a second debug module to a second program module of the computer program, where the second program module operating a second node of a different computer architecture; and initiating debug functions of at least one of the first debug module and the second debug module through a distant linker.

Methods and systems for interactive debugging in a mixed computer environment

A computing environment and techniques are provided for processing work out of order in one or more processing contexts. The processing techniques include: determining, for a processing context having an associated stack of waiting resources, whether a last-in listed resource in the stack of waiting resource is available, and if so, resuming processing of a suspended unit of work requiring the last-in listed resource; and determining, otherwise, whether an out of order execution unit of work is available for processing in the context, and if so, processing the out of order execution unit of work while the suspended unit of work awaits the last-in listed resource. Out of order execution units of work can be processed in order from a regular unit of work queue, or out of order from an out of order unit of work queue of a processing context.

Adaptive scheduling and management of work processing in a target context in resource contention

A method of parallel processing in which there is first provided a first thread which represents an independent flow of control managed by a program structure, the first thread having two states, a first state processing work for the program structure and a second state undispatched awaiting work to process; and a second thread which represents an independent flow of control managed by a program structure separate from the first thread. The method includes using the second thread to prepare work for the first thread to process and placing the work prepared by the second thread in a queue for processing by the first thread. If the first thread is awaiting work to process when the work prepared by the second thread is placed in the queue, the method includes dispatching the first thread and using it to process the work in the queue. If the first thread is processing other work when the work prepared by the second thread is placed in the queue, the method includes using the first thread to complete processing of the other work, access the work in the queue, and then process the work in the queue.

Method of using a distinct flow of computational control as a reusable abstract data object

A method is described for dynamic stitching of a new module of executable code in a parallel processing environment, where access to a data object is shared by the new module and another module previously loaded. A new data object is created for shared access by the new module and by the other module; a data freshness indicator is updated in accordance therewith. A pointer value for the data pointer associated with the other module is modified, thereby terminating reference to an old data object previously accessed and substituting reference to the new data object. A second data freshness indicator is updated in accordance with access by the other module to the new data object. The old data object is deleted when a comparison between freshness indicators shows that access to the old data object is no longer required.

Dynamic seamless reconfiguration of executing parallel software

A computer memory structure for parallel computing has a first level of hierarchy comprising a plane. The plane contains a thread which represents an independent flow of control managed by a program structure, a heap portion for data structure, a stack portion for function arguments, and local variables and global data accessible by any part of the program structure. The memory structure further has a second level of hierarchy comprising a space. The space contains two or more of the planes, with the planes in the space containing the program structure. The space further contains common data accessible by the program structure between each of the planes. A third level of hierarchy in the memory structure comprises two or more of the spaces. The spaces contain the same or different program structures, and common data accessible by the program structure between each of the spaces. The program structure comprises a library of programs and further includes a function table for each space, with the function table being adapted to exchange services with the library in each space.

Parallel software processing system

A method for allocating memory in a parallel processing computing system in which there is first provided a system memory available for parallel processing and first and second threads, each of the threads representing an independent flow of control managed by a program structure and performing different program tasks. The method includes using the first thread to request memory from the system memory; allocating to the first thread a first pool of memory in excess of the request and associating the memory pool with the second thread; using the second thread to request memory from the system memory; allocating to the second thread a second pool of memory in excess of the request and associating the memory pool with the first thread; using the first thread to request further memory from the second thread; and allocating to the first thread a portion of the second pool of memory from the second thread without making a request to the system memory. Each of the first and second memory pools contains memory portions marked by the system memory for the first and second threads. The method then includes freeing by the second thread a portion of the first memory pool marked for the first thread, and allocating to the first thread the portion of the second memory pool marked for the second thread.

High performance non-blocking parallel storage manager for parallel software executing on coordinates

A method for verifying that an integrated circuit design tool kit has not been modified in an unauthorized manner is accomplished by providing a verification procedure that, when an executable subrule of the tool kit has been selected to be part of the rule system, the executable subrule reads a table of time stamps. This table of time stamps and a key are provided, as representative data, to an authentication subrule by the executable subrule. The executable subrule and the authentication subrule perform an authentication check algorithm upon the representative data to produce remotely and locally checked data respectively. The executable subrule then provides the locally checked data to the authentication subrule which compares the locally checked data with the remotely checked data. When a match occurs between the data, the authentication subrule indicates that the executable subrule has not been modified in an unauthorized manner. When the locally checked data does not match the remotely checked data, the authentication subrule indicates that an unauthorized modification has occurred.

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Poughkeepsie, NY, United States of America

Peter Claude Elmendorf