Vlsi Technology, Inc.

Micrel, Incorporated

Koninklijke Philips Corporation N.V.

Stratos Lightware, Inc.

Peter Chambers

David R Evoy

Lonnie Calvin Goff

Joseph James Judkins

Franklyn H Story

Subramanian S Meiyappan

Scott E Harrow

Swaroop Adusumilli

Mark Eidson

William Andrew Burkland

Douglas Paul Anderson

David J Kunst

Gabriel R Munguia

Luis Torres

Steven A Martinez

Edward Michael Petryk

Roger Lee Shelton

Omer Lem Wehunt, Jr

Robert James Lewandowski

Ronald E Lange

Gary A Walker

Thomas A Lindsay

Paul Wilson

Ken Jaramillo

Thruston Awalt

David Gerard Spaniol

Ray Zinn

Michael R Crews

George Parker Crouse

Tom Lindsay

Mark Hidson

Scott Brown

Dave Evoy

An accelerator circuit is incorporated in a laser diode system for accelerating the turn-on operation of the laser diode independent of the control loop bandwidth of the laser diode system. The accelerator circuit provides a boost current to a compensation capacitor upon laser turn-on which compensation capacitor operates to establish the control loop bandwidth of the laser diode system. The boost current enables the control loop to increase the bias current to the laser diode quickly. When the laser diode reaches the desired operating point, the boost current is terminated and the control loop of the laser diode system resumes normal control of the bias current. In one embodiment, the accelerator circuit includes a timer circuit controlling a current source to implement open loop turn-on control. In another embodiment, the accelerator circuit includes a comparator circuit working in conjunction with an one-shot logic circuit for providing close loop control.

Laser turn-on accelerator independent of bias control loop bandwidth

A method in an integrated circuit for generating an address value having a contiguous address range from a first selection result and a second selection result each being an one-of-k selection result includes selecting multiple multiplication factors being power-of-two multiplication factors and the sum of the multiplication factors being equal to k; shifting the first selection result towards the most significant bit by each of the multiplication factors to generate multiple shifted input values where each shifted input value is shifted towards the most significant bit by one of the multiplication factors; adding the shifted input values and the second selection result; and generating the address value having a contiguous address range. The method can be extended to combine more than two selection results by applying the shifting and addition steps in a hierarchical manner.

Address generation method for combining multiple selection results

A data decoder for decoding an asynchronous incoming data stream includes a bit engine receiving information describing the incoming data stream and generating a decoded data stream. In one embodiment, the bit engine includes a best-fit bit analysis block performing a pattern match operation for each data bit of the incoming data stream using the information describing the incoming data stream. The best-fit bit analysis block is operative to find a pattern of data bits that best matches the data bits in the incoming data stream. The bit engine further includes a missing bit insertion block to insert a dummy bit for each data bit where the best-fit bit analysis block cannot find a pattern match. An error correction block performs forward error correction on the decoded data stream, including the dummy bits, to generate a corrected outgoing data stream.

Adaptive decoder for decoding an asynchronous data stream

A method based on a circuit coupled to an input-output bond pad (I/O pad) in an integrated circuit including an input buffer, an output buffer and a pad management circuit. The pad management circuit receives a first data signal, a first output enable signal, and a configuration signal indicative of the connection state of the I/O pad, and generates a second data signal and a second output enable signal. When the configuration signal indicates the I/O pad is to be connected to a package pin, the pad management circuit couples the first data signal as the second data signal and couples the first output enable signal as the second output enable signal. When the configuration signal indicates the I/O pad is to be left unconnected, the pad management circuit asserts the second output enable signal and generates the second data signal having a predetermined value.

Input/output circuit for handling unconnected I/O pads

A device for processing a digital input value includes a first memory portion having stored thereon Q delimiter values where the Q delimiter values divide the range of the N-bit digital input value into Q+1 regions and at least a first region and a second region are of unequal sizes, a second memory portion has stored thereon a look-up table storing Q+1 sets of coefficients for performing numerical value conversion of the digital input value to a digital output value in a second, natural unit, and an arithmetic logic performing numerical value conversion using the N-bit digital input value and the selected coefficient pair. The N-bit digital input value is compared with the Q delimiter values to determine a respective one of the Q+1 regions in which the N-bit digital input value lies. The look-up table is indexed according to the respective region to provide the selected coefficient pair.

Laser controller integrated circuit including variable resolution data processing device

An automatic power control system provides a control signal that regulates the output power of at least one laser diode. Coarse adjustment of the control signal is provided by a first means, preferably a digital variable resistor, while fine adjustment and compensation is provided by a second means, preferably by a digital-to-analog converter that receives an input signal proportional to a sensed control system parameter. The control system includes an operational amplifier having a first input coupled to sense output power, and a second input coupled to a DAC to provide finer resolution control. Memory can store system parameter or system parameter variations that can be coupled to the DAC and/or variable resistor to enhance system stability over ambient variations.

Automatic control of laser diode current and optical power output

A device for performing numerical value conversion of a digital input value in a first unit to a second, natural unit where the digital input value is a digitized value of a first measurement parameter includes a look-up table storing an array of coefficients for performing the numerical value conversion for multiple measurement parameters. The look-up table is indexed using a first parameter indicative of the first measurement parameter to provide a selected coefficient. The device further includes an arithmetic logic unit (ALU) receiving the digital input value and the selected coefficient and performing the numerical value conversion based on a first equation and the selected coefficient to compute a digital output value. The device also includes a saturation-limit circuit coupled to receive the digital output value from the arithmetic logic unit and provide a predetermined output value when the digital output value exceeds a predetermined maximum value.

Numerical value conversion using a saturation limited arithmetic logic unit supporting variable resolution operands

A device for performing numerical value conversion of a digital input value in a first unit to a second unit being a natural unit includes a look-up table storing an array of coefficients for performing the numerical value conversion. The look-up table is indexed using a first parameter to provide a selected coefficient. An arithmetic logic unit (ALU) is coupled to receive the digital input value and the selected coefficient and perform the numerical value conversion based on a first equation using the selected coefficient to compute a digital output value in the second unit. The first unit can be an arbitrary ADC unit and the second unit is a natural unit of physical measurement, such as volts, amperes, degree Centigrade. Furthermore, the device can be used to perform numerical value conversion from the arbitrary unit to the natural unit having a linear or a non-linear relationship.

Numerical value conversion using a look-up table for coefficient storage

A circuit in an integrated circuit having an input terminal to be coupled to a resistor network for selecting one of multiple digital states in the integrated circuit includes a voltage decode circuit, a control circuit and a power-up control circuit. The first input terminal receives an input voltage having a voltage value associated with the multiple digital states. The voltage decode circuit receives the input voltage and generates a voltage decode signal indicative of the voltage value of the input voltage. The control circuit receives the voltage decode signal and generates an output control signal accordingly where the output control signal selects one of the multiple digital states. The power-up control circuit provides power to the resistor network, the voltage decode circuit and the control circuit for determining the selected digital state and disconnects power to those circuits after the selected digital state is determined.

Power saving method in an integrated circuit programming and control circuit

A circuit coupled to an input-output bond pad (I/O pad) in an integrated circuit including an input buffer, an output buffer and a pad management circuit. The pad management circuit receives a first data signal, a first output enable signal, and a configuration signal indicative of the connection state of the I/O pad, and generates a second data signal and a second output enable signal. When the configuration signal indicates the I/O pad is to be connected to a package pin, the pad management circuit couples the first data signal as the second data signal and couples the first output enable signal as the second output enable signal. When the configuration signal indicates the I/O pad is to be left unconnected, the pad management circuit asserts the second output enable signal and generates the second data signal having a predetermined value.

A circuit and method for programming and control of an integrated circuit includes a control pin receiving an applied input voltage selected from a set of predetermined programming voltages and an on-chip control voltage decode circuit to select one of multiple programming states for the integrated circuit based on the applied input voltage. In one embodiment, an off-chip voltage divider is used to establish the set of predetermined programming voltages. The on-chip control voltage decode circuit includes a voltage divider to generate comparison voltage levels for detecting the voltage level of the input voltage for selecting the desired programming state. The comparison voltage levels include voltages having voltage values that are midway between pairs of adjacent programming voltages. The voltage decode circuit includes a control circuit receiving comparison results from comparators and generating an output control signal for selecting the desired digital state based on the comparison results.

Analog control of a digital decision process

A circuit in an integrated circuit having input terminals coupled to a resistor network for selecting one of multiple digital states includes a tri-state circuit, a multiplexer, a comparator and a control circuit. A DAC can be used to generate a set of comparison voltage levels. The circuit detects the power connection and the resistance values of at least two resistors in the resistor network having a third resistor of fixed resistance. The resistance values for the two resistors are selected from a set of resistance values corresponding to the number of digital stages which can be programmed on each terminal. The power connection option doubles the number of digital stages to be programmed on each terminal. Thus, multiple programming states can be assigned to each control pin of an integrated circuit and a large number of programming states can be programmed using a small number of control pins.

Programming and control of an integrated circuit using an externally connected resistor network

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Phoenix, AZ, United States of America

Peter Chambers