Santel Networks, Inc.

Broadcom Corporation

Hrl Laboratories, LLC

Aspendos Communications

Fairchild Semiconductor Corporation

Beceem Communications Inc.

Peter Capofreddi

Derek Keith Shaeffer

Sriraman Dakshinamurthy

Korhan Titizer

Mohamed Mostafa

Dennis Pu

Arvin Ramesh Shahani

Anu Pisipaty

Devices and methods are provided for generating a regulated output voltage with improved line rejection based on an input voltage and a reference voltage. The device may include a pass transistor and a replica transistor, wherein source ports of the pass transistor and the replica transistor are coupled to the input voltage, a drain port of the pass transistor is coupled to the output voltage, and a gate port of the pass transistor is coupled to a gate port of the replica transistor. The device may further include a coupling circuit configured to couple current from the drain port of the replica transistor to the gate port of the replica transistor, the coupling circuit further configured to control voltage on the drain port of the replica transistor based on the reference voltage.

Voltage regulator with improved line rejection

Embodiments of the present disclosure provide systems and methods for estimating gain and phase error in a wireless transmitter. Embodiments of the present disclosure provide a gain and phase controller that uses a digital gain and phase estimator to jointly estimate both gain and phase. The forward and feedback signals of a wireless transmitter are digitized using analog to digital (ADC) converters. The digital signals are correlated with each other to dynamically extract gain and phase estimates of the loop. The gain and phase estimates are used to correct gain and phase errors in the wireless transmitter.

Closed loop power control for a wireless transmitter

A method and apparatus of compensating for an asymmetric frequency response of a radio are disclosed. One method includes estimating a slope control signal, the slope control signal indicating a slope of a frequency response of an amplifier chain of the radio. A difference between gain at positive frequencies and gain at negative frequencies of a complex baseband signal is adjusted with the slope control signal, wherein the complex signal includes an I component and a Q component. The adjusted complex baseband signal is frequency up-converted into a radio signal. The radio signal is amplified by the amplifier chain. The amplified radio signal is transmitted.

Compensation of an asymmetric frequency response of a radio

A method and a device for spectrally shaping nonlinear intersymbol interference (NLISI) in an oversampling digital-to-analog converter are disclosed. At least one higher-order shaper circuit is provided, so as to shape NLISI, causing energy associated with NLISI to fall outside a signal band. The signal-to-noise ratio achieved is better than signal-to-noise rations obtained in prior art NLISI reducing methods and devices.

Oversampling D/A converter and method for shaping nonlinear intersymbol interference in an oversampling D/A converter

A transconductance cell is disclosed that includes a first transistor and a second transistor. A regulator regulates an average voltage in response to a reference voltage, where the average voltage corresponds to the average of a voltage at a bias terminal of the first transistor and a voltage at a bias terminal of the second transistor. A mixer including the transconductance cell is also disclosed. In the mixer, the transconductance cell receives a differential input voltage and produces a differential output current. The mixer also includes one or more switches that multiply the differential output current with an oscillator signal. A method is disclosed that includes measuring an average voltage of a voltage at a bias terminal of a first transistor and a voltage at a bias terminal of a second transistor and regulating the average voltage responsive to the measured average voltage and a reference voltage.

Increasing the linearity of a transconductance cell

A delta-sigma modulator that provides improved SNR performance in applications such as low-power mobile wireless communications and high frequency radar applications is disclosed. Multiple comparators, each comprising a sequence of three latches, connect the modulator's input filter circuitto the modulator's output interfaces, providing quantization of the integrated, filtered signal provided by the filter circuit. A clock signal having a cycle period Tenables a first latchconnected to the signal input of each comparatorto provide a digital signal to the signal input of a second latch. The second latchsupplies a digital signal to a third latchin the sequence, in response to the signal received from the first latch, by a lagged clock signal derived from the given clock signal Tby providing a first lag time Twhere T/2&#x2267;T&#x3e;0. A third latch in the sequence is enabled by a clock signal having a second lag time T=T/2+T, and the delay T&#x3c;&#x3c;T/2. When T=T/2 the inverted clock signal supplied to the second latch is delayed and supplied to the third latch. When T=Tthe delayed clock signal supplied to the second latch is inverted and supplied to the third latch.

Method and apparatus for improving the performance of delta-sigma modulators

Circuits, methods, and systems are provided for opening a primary feedback loop in a transmitter. An auxiliary feedback loop can be closed when the primary feedback loop is opened, and a controller can match a gain of the primary feedback loop to another gain in the transmitter.

Method and apparatus for opening a feedback loop

A circuit is provided that includes a Cartesian feedback loop. The Cartesian feedback loop includes one or more operational amplifiers. At least one of the operational amplifiers includes two or more cascaded amplifier stages and one or more bypass amplifier stages. The bypass amplifier stages are connected in parallel with the cascaded amplifier stages.

Low phase shift implementation of the baseband circuitry of a Cartesian feedback loop

An apparatus for coupling a wideband current signal between two different potentials. The apparatus incorporates a capacitor for providing a signal path for a high frequency signal from a first potential to a second potential. The apparatus further incorporates a current mirror for providing a signal path to a low frequency signal from the first potential to the second potential.

Mechanism for coupling a wideband current signal between two different potentials

An analog FIR filter that processes multiple output samples in parallel is disclosed. The simultaneous parallel processing of multiple samples permits improved sampling rate and improved accuracy as compared to prior art filters.

Analog fir filter with parallel interleaved architecture

An improved thermometer-to-binary coder in which the bits of the thermometer code are used to directly generate the binary code without using an intermediate one-hot code.

Method and apparatus for low power thermometer to binary coder

An analog discrete-time filter that processes multiple output samples in parallel is disclosed. The simultaneous parallel processing of multiple samples permits improved sampling rate and improved accuracy as compared to prior art filters.

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San Francisco, CA, United States of America

Peter Capofreddi