Agere Systems Inc.

Cisco Technology, Inc.

Peter C Metz

Craig S Appel

Donald Raymond Laturell

Vladimir Sindalovsky

Christopher John Abel

Sanjay Sunder

Joseph V Pampanin

Baiying Yu

Lane Allen Smith

John M Khoury

Kalpendu Shastri

Gregory W Sheets

Kadaba Lakshmikumar

Bipin Dama

James D Chlipala

Abhishek Duggal

Embodiments provide for a tunable driving circuit by monitoring a frequency of a ring oscillator of an electrical integrated circuit connected to an optical modulator to determine operational characteristics of the electrical integrated circuit; setting, based on the operational characteristics, a driving voltage for a plurality of tunable inverters and a plurality of fixed gain inverters that control the optical modulator, wherein each tunable inverter of the plurality of tunable inverters is connected in parallel with a corresponding fixed gain inverter of the plurality of fixed gain inverters on one of a first arm and a second arm connected to the optical modulator; and setting an amplification strength for the plurality of tunable inverters based on the operational characteristics.

Tunable driver

The present disclosure provide for active boost in an electrical driver via a frequency comparator, configured to determine operational characteristics of an electrical circuit connected to an optical modulator based on a frequency difference between a ring oscillator and the clock signal; an electrical driver configured to drive a phase shift of a first optical signal carried on a first arm relative to a second optical signal carried on a second arm of an optical modulator, the electrical driver comprising: a first signal pathway, connected to the first arm of the optical modulator, wherein the first signal pathway includes: an adjustable gain inverter, electrically connected to first and second nodes; a fixed gain inverter, electrically connected to the first and second nodes; an inductor electrically connected between the second node and a third node; and a non-inverting amplifier connected between the third node and the first node.

Optical driver with active boost

An optical modulator is configured to include multiple modulating sections formed along each arm and create a unary-encoded optical output signal by driving the number of sections required to represent the data value being transmitted (e.g., three sections driven to represent the data value '3', four sections driven to represent the data value '4'). An auxiliary modulating section, isolated from the optical signal path, is included for creating a path for current flow in situations where only an odd number of modulating sections are required to represent the data. The activation of the auxiliary modulation section minimizes the current imbalance that would otherwise be present along a common node of the arrangement.

Optical modulator utilizing unary encoding and auxiliary modulator section for load balancing

Clock and data recovery circuitry includes an interleaved sampler having multiple integrators, where at least one of the integrators integrates the input data for at least two unit intervals (UIs). One embodiment includes a four-way interleaved sampler, where each integrator in the sampler integrates the input data for two UIs, where each integrator is sampled at or near the middle of its two-UI integration cycle. In an exemplary 10-GHz system, the reset cycle of each integrator may begin many tens of picoseconds after the data is sampled. Since the signal is sampled near the center of the integration cycle and is not highly proximate to the time of the integrator reset, the latch signal has a window of uncertainty extending into the length of a data bit cell with little possibility of latching erroneous data. The sensitivity of the clock recovery circuitry may be optimized by centering the latch function over the time of highest signal level, thereby maximizing signal-to-noise ratio.

Clock and data recovery with extended integration cycles

Methods and apparatus are provided for delay line control using receive data. A delay in a Delay-Locked-Loop circuit is controlled by obtaining a plurality of samples of one or more received signals for each unit interval; determining a data eye width in the one or more received signals; and adjusting a delay of at least one clock signal based on the data eye width. For example, the measured data eye width can be compared to a predefined value, such as a desired or ideal value. Generally, the delay is not adjusted in accordance with the present invention until the Delay-Locked-Loop circuit has reached a locked condition based on one or more predefined criteria.

Method and apparatus for delay line control using receive data

Methods and apparatus are provided for improved digital-to-analog conversion. The disclosed digital-to-analog converter comprises a master digital-to-analog converter that generates a master analog value, and a slave digital-to-analog converter that generates a slave analog value that is based on the master analog value. The slave analog value can be, for example, substantially proportional to the master analog value. The master D/A converter can be varied during a coarse tuning mode, while the input to the slave D/A can be fixed, for example, to an approximately mid-range value until the master analog value satisfies one or more predefined conditions. Thereafter, during a fine tuning mode, the slave D/A converter can be varied, while the master D/A converter is fixed, so that the output Y is equal to a desired value (within a specified tolerance).

Method and apparatus for master/slave digital-to-analog conversion

Methods and apparatus are provided for sigma-delta delay control in a Delay-Locked-Loop that employs a delay line to generate a clock signal based on a reference signal. A first value is generated if a clock signal has a time lead relative to a reference signal; and a second value is generated if a clock signal has a time lag relative to a reference signal. The first and second values are accumulated to generate an N bit digital word; and the N bit digital word is reduced to an M bit digital word, where M is less than N. Thereafter, the M bit digital word can be converted to an analog bias signal. The reducing step can be performed, for example, by a sigma-delta modulator. The high frequency quantization noise generated by the sigma-delta modulator can be filtered using a low pass filter. The converting step can be performed by a digital-to-analog converter, such as a master/slave digital-to-analog converter.

Method and apparatus for sigma-delta delay control in a delay-locked-loop

Methods and apparatus are provided for trimming a phase detector in a delay-locked-loop. A latch that evaluates a phase offset between two signals is trimmed by applying two signals to the latch that are substantially phase aligned; obtaining a phase offset between the two signals measured by the latch; and adjusting a trim setting of one or more buffers associated with the two signals until the phase offset satisfies one or more predefined criteria. The two signals can be a clock signal and an inverted version of the clock signal. The two signals can be a source of phase aligned data generated from a single clock source.

Method and apparatus for trimming a phase detector in a delay-locked-loop

A circuit (e.g., a receiver) has a delay loop (e.g., a voltage-controlled delay loop) and (at least) two phase detectors (PDs), where each PD compares a different pair of clock signals generated by the delay loop. The outputs of the different PDs are then used to generate a control signal for adjusting the delays provided by the delay elements in the delay loop. In one implementation, the control signal indicates that a delay adjustment should be made only if both PDs agree on that adjustment. This multiple-PD technique can reduce jitter that could otherwise result from a non-50% duty cycle in the reference clock signal used by the delay loop to generate its multiple clock signals.

Multiple phase detection for delay loops

A method and apparatus for detecting the phase difference between an input data signal and a local clock signal is provided. An input data signal is frequency divided and then fed through a series connection of a pair of data latches. Signals provided at the input and outputs of the pair of the data latches are exclusively-ORed to provide a variable width pulse signal and a reference pulse signal that may be used in a phase-locked loop to align the local clock with the input data signal in a predetermined phase relationship. A re-timed data signal is provided by inputting the input data signal to a data latch clocked with an inverted phase-aligned clock signal.

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Macungie, PA, United States of America

Peter C Metz