Ncr Corporation

Fairchild Camera and Instrument Corp.

Peter C Chen

Jerome Cohen

Ronald W Brower

Tuh-Kai Koo

John K Stewart, Jr

Alex Au

A static RAM cell (11) is constructed utilizing low resistivity positive and negative power supply leads (13,14), thus eliminating the problem of instability of the data stored within the cell. The negative power supply lead is formed of a first layer of low resistivity polycrystalline silicon/tantalum silicide, and the positive power supply lead is formed of a second layer of polycrystalline silicon. The use of a low resistivity negative power supply lead causes the voltage drop on the negative power supply lead to be substantially reduced as compared with prior art devices, thereby providing during the read operation substantially equal voltages to the gates of the two bistable transistors of each cell, thus eliminating the problem of instability during reading. Depletion load devices (11,12) are formed utilizing the layer of polycrystalline silicon as the source, drain and channel and the layer of polycrystalline silicon/tantalum silicide as the gate. In this manner, silicon area is not required to form the depletion load devices, thus minimizing cell size.

Static RAM cell

A method of manufacturing a silicon gate MIS device providing automatic formation and alignment of the gate structure during formation of adjacent impurity regions. In a preferred embodiment, the process is for the gate structure and source and drain of silicon gate FETs. The layered gate constituents-- typically oxide and silicon-- are formed on a semiconductor wafer. A photoresist mask which is larger than the desired gate size is formed on the silicon and the silicon is etched to a predetermined size beneath the overhanging mask. A deposition mask in the form of the photoresist mask or the gate silicon oxide and which is of the same size as the photoresist mask, is used to control the deposition of impurities within predetermined surface areas of the substrate which are spaced a predetermined distance from the silicon gate boundaries. By diffusion, the impurities are driven into the substrate to the desired depth to complete the source and drain, which are thereby driven laterally into coincidence with the gate boundaries. The aligned, non-overlapping relationship of the gate structure with the source and drain minimizes gate overlap capacitance.

Process for minimum overlap silicon gate devices

An adhesion-enhancing technique for preparing the surface of a polycrystalline silicon body to receive organic photoresist. In an exemplary procedure, the polysilicon is placed in an oxygen plasma chamber operating under rf power of about 90 milliwatts per cubic centimeter of chamber volume and a pressure of approximately 1 torr for 10 minutes to form an adhesion-enhancing oxide monolayer on the polysilicon.

Method for enhancing the adhesion of photoresist to polysilicon

An improvement of the prior art method of processing large scale integrated (LSI) semiconductors is disclosed, wherein an etching procedure, which was previously performed as the final processing step, is now done at an earlier stage to preclude damage to the surface of the wafer on which the active devices are formed. In the prior art method of fabricating an active device on a semiconductor wafer, an undesirable layer of field oxide manifests itself on the reverse side when the field oxide is grown on the obverse or principal side of the wafer. The prior processing philosophy was to allow the oxide layer to remain on the wafer until after the processing was completed and, as a final step, the undesired oxide coating was removed. This was done by carefully placing the wafer in a pool of etchant so that only the reverse side is etched. Since the wafer is only about 12 mils thick, the operator had to exercise extreme caution in placing the wafer in the etchant to prevent the etchant from creeping up the thickness dimension of the wafer and thus etching the obverse side. Our novel method contemplates modifying the processing steps of the prior art by removing the undesired field oxide before the circuits or active devices have been completely formed, when the wafer may be completely immersed in the etchant without damaging or etching areas on the active portion of the wafer.

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Sunnyvale, CA, United States of America

Peter C Chen