Altera Corporation

Peter Boyle

Iliya G Zamek

Adam J Wright

Chiakang Sung

Joseph Huang

Yan Chong

Eric Choong-Yin Chang

Zhe Li

Nafira Daud

Lawrence David Smith

Qi Chen

Binh Vo

James L Drewniak

Bozidar Krsnik

Sandeep Kamalakar Reddy Chandra

Kaiyu Ren

John DiCosola

Laiq Chughtai

Xiaohe Chen

Eugene V Gomez

Wan-Pin Hung

Seng Yew Lim

A method for accurately determining the shape of currents in a current spectrum for a circuit design is provided. The method includes determining timing and power consumption characteristics. In one embodiment, timing characteristics are provided through a electronic design automation tool. The timing characteristics yield a current pulse time width. In another embodiment, power consumption characteristics are provided by an EDA tool. The power consumption characteristics yield a current pulse amplitude. The shape of the current pulse is obtained by incrementally processing a power analyzer tool over relatively small time increments over one or more clock cycles while capturing the switching nodes of a simulation of the circuit design for each time increment. In one embodiment, the time increments are one nanosecond or less.

Prediction of dynamic current waveform and spectrum in a semiconductor device

Delay associated with each of two signals along respective transmission paths is accurately measured using a delay measurement circuit that is fabricated in situ on the actual device where the circuitry for propagating the two signals is fabricated. Thus, the measured delay associated with each of the two signals is subject to the same fabrication-dependent attributes that affect the actual circuitry through which the two signals will be propagated during operation of the device. The skew between the two signals is quantified as the difference in the measured delays. Coarse and fine delay modules are defined within the transmission path of each of the two signals. Based on the measured skew between the two signals, the coarse and fine delay modules are appropriately set to compensate for the skew. The appropriately settings for the coarse and fine delay modules can be stored in non-volatile memory elements.

Method and apparatus for minimizing skew between signals

A method for accurately determining the shape of currents in a current spectrum for a circuit design is provided. The method includes determining timing characteristics and power consumption characteristics for the circuit design. In one embodiment, the timing characteristics are provided through a electronic design automation tool. The timing characteristics yield a current pulse time width. In another embodiment, the power consumption characteristics are provided by an EDA tool. The power consumption characteristics yield a current pulse amplitude. The shape of the current pulse is obtained by incrementally processing a power analyzer tool over relatively small time increments over one or more clock cycles while capturing the switching nodes of a simulation of the circuit design for each time increment. In one embodiment, the time increments are one nanosecond or less. From the timing characteristics and the power consumption characteristics a time domain current waveform is constructed, which can be converted to the frequency domain.

A method for determining a current spectrum for a circuit design is provided. The method includes determining timing characteristics and power consumption characteristics for the circuit design. From the timing characteristics and the power consumption characteristics a time domain current waveform is constructed. The time domain current waveform is then converted to a frequency domain current waveform. With the frequency domain waveform, one skilled in the art can then identify a location and an amount of decoupling capacitors for a printed circuit board housing the circuit design based on the frequency domain current waveform. A computing system configured to perform the method is also provided.

Techniques are provided for isolating failed routing resources on a programmable circuit. Failing test patterns and the test logs are fed to a Statistical Failure Isolation (SFI) tool. The SFI tool extracts failing paths from the test patterns. A statistical analysis is performed on interconnect resources related to failing paths. The resources on the paths are then tallied to create a histogram of resources. These resources are then be fed into an Adaptive Failure Isolation (AFI) tool to auto-generate verification patterns. A tester uses the verification patterns to isolate failed interconnect resources.

Functional failure analysis techniques for programmable integrated circuits

Integrated circuits contain core logic that is powered using a power supply signal. The core logic contains simultaneously switching circuitry. The simultaneously switching circuitry contributes to noise on the power supply signal. Balancing circuitry may be provided on the integrated circuit to compensate for the simultaneously switching circuitry in the core logic. The balancing circuitry may receive an input signal that is out of phase with respect to the input to the core logic. As the balancing circuitry switches out of phase with the simultaneously switching circuitry of the core logic, the noise contribution from the core logic is compensated and power supply noise on the power supply signal is minimized.

Integrated circuits with jitter-reducing balancing logic

Method and apparatus for quantifying and minimizing skew between signals

Computer-aided design tools analyze a custom logic design for a programmable logic device integrated circuit. The tools identify distinct clock domains in the design. The tools also identify which of the clock domains are synchronous. The tools examine the synchronous clock domains to determine which of the clock domains have required fixed phase relationships. Clocks for clock domains that do not have required fixed relationships can be adjusted in phase to minimize power supply simultaneous switching noise. Noise may be minimized by making clock phase adjustments using a programmable phase-locked loop circuit.

Methods for reducing power supply simultaneous switching noise

Methods and apparatus for designing and producing programmable logic devices are provided. A logic design system may be used to produce configuration data containing alternative configuration memory settings each of which is optimized for programmable logic devices with different performance characteristics. During manufacturing, programmable logic devices are tested to identify their performance characteristics. A bin code is stored in non-volatile memory in each device to specify which performance characteristics are associated with that device. During programming, the bin code of a given device is used to decide which of the alternative configuration memory settings are to be discarded. The retained subset of the configuration data is loaded into configuration memory in the given device.

Programmable logic device with performance variation compensation

A jitter calculator engine that includes a core effects module, an input/output (I/O) module, and a phase lock loop (PLL) module is provided. The core effects module estimates core jitter caused by noise effects impacting a core clock network. The I/O module estimates I/O input pin switching effects on a clock network input signal. In one embodiment, the I/O module identifies a relative frequency of switching by I/O pins in the circuit design. The PLL module estimates an effect of a PLL on a signal delivered to the PLL from an I/O pin. The PLL module accounts for I/O input pin switching effects and core jitter. The jitter calculator engine may be in communication with a database and the different designs evaluated may be stored in the database so that the database becomes a repository for the different designs and may provide useful information for future designs.

Growing community of inventors

Mountain View, CA, United States of America

Peter Boyle