Infineon Technologies Ag

Infineon Technologies Austria Ag

Peter Bogner

Michael Kropfitsch

Herwig Wappis

Jens Barrenscheen

Franz Kuttner

Martin Pernull

Jochen Oliver Schrattenecker

Jaafar Mejri

Gerhard Maderbacher

Dirk Hammerschmidt

Rainer Stuhlberger

Luca Petruzzi

Florian Starzer

Oliver Frank

Guenter Haider

Thomas Sailer

Andrea Cristofoli

Dietmar Straeussnigg

Alexander Melzer

Juergen Schaefer

Emanuele Bodano

Hubert Rothleitner

Joachim Pichler

Christian Reindl

Marco Faricelli

David Astrom

Sven Derksen

Martin Wiessflecker

Andreas Kalt

Josef Niederl

Mark Schauer

Francesco Santoro

Clifford Fyvie

Niranjan Reddy Suravarapu

Christoph Affenzeller

Bernhard Eisgruber

Dario Vagni

An analog-to-digital converter (ADC) circuit comprises one or more most-significant-bit (MSB) capacitors having first ends connected to a voltage comparator and one or more least-significant-bit (LSB) capacitors having first ends connected to the comparator. The circuit further comprises a first switching circuit for each MSB capacitor, configured to selectively connect the second end of the respective MSB capacitor to (a) an input voltage, for sampling, (b) a ground reference, during portions of a conversion phase, and (c) a first conversion reference voltage, for other portions of the conversion phase. The circuit still further comprises a second switch circuit, for each LSB capacitor, configured to selectively connect the second end of the respective LSB capacitor between (d) the ground reference, during portions of the conversion phase, and (e) a second conversion reference voltage, for other portions of the conversion phase, the second conversion reference voltage differing from the first.

Passive sample-and-hold analog-to-digital converter with split reference voltage

In accordance with an embodiment, a method for monitoring a data converter configured to convert data using a calibration determined by a calibration data record includes calibrating the data converter in order to determine a corresponding multiplicity of time associated calibration data records at a multiplicity of different times; and determining a state of the data converter based on comparing at least one of the multiplicity of time associated calibration data records with a comparison data record.

Methods, apparatuses and systems for data conversion

Sampling circuits and methods for sampling are provided. In a first operating phase, sampling capacitors are coupled to inputs, and in a second operating phase, to a common-mode signal.

Sampling circuit and sampling method

A method includes: receiving a reflected radar signal including a first radar chirp signal during a first chirp time period and a second radar chirp signal during a second chirp time period; downconverting the reflected radar signal to form a baseband signal; adding a DC offset to the baseband signal to form a DC offset baseband signal, adding the DC offset including adding a first DC offset to the baseband signal during the first chirp time period, and adding a second DC offset to the baseband signal during the second chirp time period, where the first DC offset is different from the second DC offset; and digitizing the DC offset baseband signal using an analog-to-digital converter to form a digitized baseband signal.

System and method for receiving a radar signal

In some examples, an integrated circuit device includes a sampling switch configured to sample an input signal. The integrated circuit device also includes a first evaluation unit configured to receive the sampled input signal from the sampling switch and evaluate the sampled input signal. The integrated circuit device further includes a second evaluation unit configured to receive the sampled input signal from the sampling switch and evaluate the sampled input signal. The sampling switch is configured to deliver the sampled input signal to the first evaluation unit and deliver the sampled input signal to the second evaluation unit.

Using a sampling switch for multiple evaluation units

A circuit having capacitors, and corresponding method. A circuit and corresponding methods are provided. A controller causes a first capacitor to be connected to an input connection in a first operating phase, charge to be transferred from the first capacitor to a second capacitor in a second operating phase and charge to be transferred from the second capacitor to a processing circuit in a third operating phase. The input connection and the second capacitor belong to different voltage domains.

Circuit with capacitors and corresponding method

A switched-capacitor analog-to-digital converter (ADC) includes: a main digital-to-analog converter (DAC) circuit; a comparator coupled to the main DAC circuit and configured to determine whether the input to the comparator exceeds a pre-determined threshold; and a supplementary DAC circuit coupled to the main DAC circuit, wherein the switched-capacitor ADC is configured to operate in at least one of a first mode or a second mode, wherein in the first mode for measuring an offset of the switched-capacitor ADC, the supplementary DAC circuit is configured to shift a voltage at an output of the main DAC circuit by a first value having a first polarity, and wherein in the second mode for measuring a full-scale gain error of the switched-capacitor ADC, the supplementary DAC circuit is configured to shift the voltage at the output of the main DAC circuit by a second value having a second polarity opposite the first polarity.

Analog-to-digital converter with a supplementary digital-to-analog converter for offset and gain error measurements

In accordance with an embodiment, a method of monitoring a data converter includes determining a multiplicity of time-associated linearity parameters that describe a linearity of the data converter at a multiplicity of different times, and determining a state of the data converter based on comparing at least one linearity parameter of the multiplicity of time-associated linearity parameters with a comparison parameter.

Methods, devices and systems for data conversion

A method and an apparatus for determining the suitability of a test delay value between comparator decisions of a comparator circuit of an asynchronous successive approximation analog/digital converter and a method for determining an optimized delay value of a comparator of an asynchronous successive approximation analog/digital converter are provided.

Method and apparatus for analog/digital conversion

In accordance with an embodiment, a method for calibrating at least two analog-to-digital converters includes feeding an analog predefined signal to the at least two analog-to-digital converters; converting the analog predefined signal into at least two converter-associated digital values using the at least two analog-to-digital converters, wherein the converting is based on a received clock signal; and adapting a converter-specific time delay based on the at least two converter-associated digital values.

Method, device and system for analog-to-digital conversion

Measurement apparatuses and methods are described. A measurement input is coupled with a first terminal of a capacitance via a first switch, and a reference voltage is coupled with the first terminal of the capacitance via a second switch. A measurement circuit is coupled to a second terminal of said capacitance.

Measurement apparatus

A circuit for processing an input-signal voltage, and including an input capacitance coupled between an input node of the circuit and a sense node of a comparator; a reference capacitance coupled to the sense node of the comparator; and a common mode switch coupled between the sense node and a reference node of the comparator. The circuit is configured to have the input capacitance set to a reference input voltage while the common mode switch is closed, and the input node set to the input-signal voltage while the common mode switch is open. The reference capacitance includes a plurality of capacitances, at least one of which is provided as a switched capacitance that is selectively controllable to configure the plurality of capacitances. A switched capacitance controller is configured to control the switched capacitance so as to compensate, at the sense node, a comparator offset voltage.

Circuit for processing an input-signal voltage

Filters are discussed where a first window function and a second window function are applied to a digital input signal, wherein a window length of the first window function is longer than a window length of the second window function. The results of this windowing are integrated.

Decimation filter

A sensor device includes an implantable sensor unit, a transponder unit, and a wired connection flexibly and electrically connecting the implantable sensor unit and the transponder unit. The implantable sensor unit is adapted to be implanted into a body. The implantable sensor unit includes a comparator and a sensor adapted to sense a characteristic of the body in vivo. The sensor is adapted to supply an analog signal to a first input of the comparator. The transponder unit is adapted to supply a control signal to the implantable sensor unit and to receive an output signal of the comparator. The implantable sensor unit is adapted to supply an analog approximation signal to a second input of the comparator in response to the control signal. The wired connection is adapted to transmit the control signal and the output signal of the comparator.

Implantable sensor device adapted to sense a characteristic of a body in vivo

A switching circuitry is configured to provide, during an ON-State, a connection between a first port and second port and to electrically disconnect, during an OFF-State, the first port from the second port. The switching interface comprises a first and a second cascode transistor element having an applicable operational voltage and comprising a control terminal, wherein the first cascode transistor element is connected with the first port of the switching interface and wherein the second cascode transistor element is connected with the second port of the switching interface. The switching interface comprises a switching transistor element, having the applicable operational voltage and comprising a third control terminal, the switching transistor element being serially connected the first and second cascode transistor elements. A supply signal arrangement is connected to the control terminals and configured to provide control voltages to the control terminals.

Growing community of inventors

Wernberg, Austria

Peter Bogner