Lsi Logic Corporation

Peter Bendix

Jau-Wen Chen

Yoon J Huh

A semiconductor device which includes a P-well which is underneath NMOS fingers. The device includes an N-well ring which is configured so that the inner P-well underneath the NMOS fingers is separated from an outer P-well. The inner P-well and outer P-well are connected by a P-substrate resistance which is much higher than the resistance of the P-wells. A P+-diffusion ring surrounding the N-well ring is configured to connect to VSS, i.e., P-taps.

Growing community of inventors

Redwood City, CA, United States of America

Peter Bendix