Infineon Technologies Ag

Infineon Technologies LLC

Peter Beer

Carsten Ohlhoff

Ulrich Karl Klostermann

Gunnar H Krause

Martin Versen

Jochen Hoffmann

Jochen Kallscheuer

Helmut Schneider

Rainer Leuschner

Daniel Braun

Herbert Benzinger

Udo Hartmann

Thilo Schaffroth

Stephan Schroeder

Manfred Dobler

Manfred Ruehrig

Alan Morgan

Achim Schramm

Reidar Stief

Lee Nino

Embodiments of the present invention generally provide methods and apparatus for testing memory devices having normal memory elements and redundant memory elements. During a front-end testing procedure, normal memory elements that are found to be defective are replaced by redundant memory elements. During the front-end test, redundant memory elements that are found to be defective may be marked as defective by blowing associated mask fuses. During a back-end testing procedure, the results of testing a normal memory element may be masked (e.g., forced to a passing result) if the normal memory element has been replaced by a redundant memory element. Similarly, the results of testing a redundant memory element may be masked if the redundant memory element was previously found to be defective, as indicated by an associated mark fuse. By masking the test results for memory elements (normal and redundant) that have been previously found defective, the memory elements may be tested in the same manner during front-end and back-end testing.

Method and apparatus for masking known fails during memory tests readouts

Apparatus and method for checking output signals of an integrated circuit are provided. One embodiment provides a method for checking whether signals are output by a write circuit of an integrated circuit according to a predefined specification. In this context, the high precision of an external test device which is inherent to the system is used to check, within a module, that a data signal and a data sampling signal of the integrated circuit are output according to a specification.

Method and apparatus for checking output signals of an integrated circuit

An integrated memory having a plurality of memory banks includes a test circuit for functional testing of the memory. A plurality of secondary sense amplifiers are assigned to a different one of the memory banks. The test circuit includes a data generator for generating read comparison data. A plurality of comparison circuits are assigned to a different one of the memory banks to compare test data read from the assigned memory bank with the read comparison data. A first input of the respective comparison circuit can be connected to the secondary sense amplifier without interposition of the read/write data lines. A second input can be connected to the read/write data lines to receive the read comparison data supplied by the data generator. An output signal of the respective comparison circuit depends on the comparison result of a data comparison of the first and second inputs.

Integrated memory having a test circuit for functional testing of the memory

The invention relates to an integrated memory module having a memory unit and a self-test circuit, the self-test circuit being embodied in such a way as to make available test data and test addresses for testing memory areas in the memory unit and to generate defect data depending on the detection of a defect, a test circuit being provided in order to receive defect data from one or a plurality of connectable memory modules to be detected, the test circuit being configured in such a way as to store the received defect data depending on addresses assigned thereto in the memory unit.

Memory module, test system and method for testing one or a plurality of memory modules

A magnetoresistive memory element includes a stacked structure with a ferromagnetic reference region including a fixed magnetization; a ferromagnetic free region including a free magnetization that is free to be switched between oppositely aligned directions with respect to an easy axis thereof; and a tunneling barrier made of a non-magnetic material. The ferromagnetic reference and free regions and the tunneling barrier together form a magnetoresistive tunneling junction. The ferromagnetic free region includes a plurality of N ferromagnetic free layers being magnetically coupled such that magnetizations of adjacent ferromagnetic free layers are in antiparallel alignment, where N is an integer greater than or equal to two. The ferromagnetic free region further includes at least one ferromagnetic decoupling layer including frustrated magnetization in orthogonal alignment to ferromagnetic free layer magnetizations and being arranged in between adjacent ferromagnetic free layers.

Adiabatic rotational switching memory element including a ferromagnetic decoupling layer

A test circuit for testing a memory circuit has a data input line for providing test data and a comparator unit. The comparator unit is connected to the data input line and to the memory circuit for comparing the test data written into the memory circuit with the test data read from the memory area. The data input line is connected to the memory circuit via a data change circuit. The data change circuit is controllable depending on a result of a comparison in the comparator unit such that when an error occurs, subsequent test data can be written in an altered manner to the memory circuit.

Test circuit and method for testing an integrated memory circuit

A first and a second memory circuit are tested in parallel. It is possible to activate the memory circuits depending on a circuit select signal, and it is possible to apply a control signal to the first and second memory circuits. The control signal initiates a function in the respective memory circuit depending on the activation of the first or second memory circuit. In testing the memory circuits, the circuit select signal is applied to the first memory circuit and the inverted circuit select signal is applied to the second memory circuit, so that the function is initiated in the first or in the second memory circuit depending on the circuit select signal.

Test system and method for testing memory circuits

A memory chip includes an on-chip data generator, a scrambler unit for checking the correct operability of the memory cells, a repair unit, and redundant word lines that, in the case of a memory cell recognized as defective, are used instead of the word line regularly activated. The scrambler unit is connected to the repair unit and, thus, receives from the repair unit information on whether the redundant word line replacing a defective word line drives transistors of memory cells that can be connected to true bit lines or to complementary bit lines. As such, the scrambler unit can take the information as to whether a true bit line or a complementary bit line is driven through the spare word line into consideration when performing the test procedure. This provides for a more efficient performance of the test procedure. Also provided is a method for testing memory cells.

Memory chip with test logic taking into consideration the address of a redundant word line and method for testing a memory chip

A test device has an interface for connecting a memory circuit that is to be tested and for receiving fault addresses. The test device further has a fault address memory for storing fault addresses and a control unit for allocating the received fault addresses to a fault address which is to be stored. A first sequence of memory cells can be addressed with a first access time, and a second sequence of memory cells can be addressed with a second access time, in the fault address memory. The second access time is longer than the first access time. First fault addresses are received at a first data rate, and second fault addresses are received at a second data rate, via the interface. The second data rate is lower than the first data rate. The control unit stores the first fault addresses in the fault address memory on the basis of the first sequence of memory cells, and stores the second fault addresses in the fault address memory on a basis of the second sequence of memory cells.

Test device, test system and method for testing a memory circuit

A magnetic memory element including a magnetic storage element including two magnetic layers made of magnetic material, said two magnetic layers opposing each other in a parallel relationship and being vertically oriented relative to a wafer surface on which the magnetic memory element is formed, said two magnetic layers further having a magnetic anisotropy, while its magnetization vectors are magnetically coupled to at least one current line, wherein said two magnetic layers are arranged on a same side of said at least one current line, and a magnetic sensor element including at least one magnetic layer having a magnetization vector being magnetically coupled to said magnetization vectors of said two magnetic layers of said magnetic storage element, said magnetic sensor element being electrically coupled to said at least one current line.

MRAM with vertical storage element in two layer-arrangement and field sensor

It is possible to read out data in accordance with a read-out address from memory cells via bit lines and primary sense amplifiers. Each secondary sense amplifier is assigned a group of primary sense amplifiers. It is possible for the primary sense amplifiers of a group to be connected to one of the secondary sense amplifiers in each case via switching devices in order to apply the datum from one of the primary sense amplifiers to the assigned secondary sense amplifier via the switching device selected by the read-out address. For reading out data, a test control unit is provided to connect some of the switching devices in parallel depending on a test mode signal and depending on a read-out address, so that in each case one of the group of primary sense amplifiers is connected to the assigned secondary sense amplifiers.

Memory circuit and method for reading out data

One embodiment of the invention provides a method for providing defect information from an integrated memory chip having dynamic memory cells arranged on word lines and bit lines, wherein a word line group having a number of word lines may be replaced by a redundant word line group and wherein a bit line may be replaced by a redundant bit line to replace defective memory cells, wherein test data are written to the memory cells of the memory chip for the purpose of testing the memory cells, the written data being read out and compared with the previously written test data to generate first defect information items depending on the result of the comparison, the first defect information item indicating a defect if the written test data and the read-out data are different, the memory cells along one of the bit lines being read successively, the first defect information item in each case being generated for each of the read memory cells, the first defect information items being buffer-stored during the testing of the memory cells on the word line group, a second defect information item being generated, the second defect information item indicating a defect if at least one of the first defect information items indicates a defect, the second defect information item being output after the end of the read-out of the memory cells of the word line group along the bit line.

Apparatus and method for reading out defect information items from an integrated chip

A dynamic memory cell which can be selected by means of a selection signal and the content of which can be read out by means of a bit line pair with a first and a second bit line, having a storage capacitor and a first and a second selection transistor, in which case, depending on the selection signal, a first terminal of the storage capacitor can be connected to the first bit line via the first selection transistor and a second terminal of the storage capacitor can be connected to the second bit line via the second selection transistor, is provided.

Dynamic memory cell

An integrated memory circuit having a redundancy circuit for replacing a memory area having an address by a redundant memory area assigned to the redundancy circuit and method for replacing a memory area. In one embodiment, the redundancy circuit comprises one or more fuse storage elements in which the address of the memory area which is to be replaced by the redundant memory area can be set, wherein, for the purpose of setting the address, each of the fuse storage elements may be set to a first state by the respective fuse storage element being left unchanged and set to a second state by the respective fuse storage element being permanently changed, an activation fuse storage element for activating the address stored in the fuse storage elements for replacing the memory area with the redundant memory area, and a deactivation storage element for permitting or preventing replacement of the memory area having the address by the redundant memory area, wherein the deactivation storage element is connected to the fuse storage elements in such a way as to prevent replacement of the memory area if each of the fuse storage elements has been permanently changed and set to the second state.

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Tutzing, Germany

Peter Beer