Mosaid Technologies Corporation

Conversant Intellectual Property Management Incorporated

Advanced Memory International, Inc.

Mitel Corporation

Mosaid, Inc.

Other

Accelerix Limited

Novachips Canada Inc.

Conversant IP Management Inc.

Peter B Gillingham

Graham A Allan

Richard C Foss

Jin-Ki Kim

Valerie L Lines

Robert F Harland

Bruce Millar

Cormac Michael O'Connell

Abdullah Ahmed

Robert McKenzie

Hong Beom Pyeon

Randy R Torrance

Douglas I Perry

John K Wu

David Alan Brown

Stanley Jeh-Chun Ma

Peter P Ma

Lidong Chen

Atsushi Wada

Masami Mitsuhashi

Dennis A Fielder

James H Derbyshire

Brent Keeth

David V James

Roger Colbeck

Roland Schuetz

William Francis Petrie

Tomasz Wojcicki

Karl Skjaveland

Troy A Manning

Taiji Ema

Terry R Lee

Alan S Roth

Kevin J Ryan

Paul W Demone

Peter Vlasenko

Yoshikazu Morooka

Henry Stracovsky

Shigetoshi Takeda

Desi Rhoden

Donald N North

Hans A Wiggers

David B Gustavson

Hunsam Jung

Gregg M Shimokura

Randall R Torrance

Jan H Erkku

Philip S Shaer

Jean Crepeau

A clock mode configuration circuit for a memory device. A memory system includes any number of memory devices serially connected to each other, where each memory device receives a clock signal. The clock signal can be provided either in parallel to all the memory devices or serially from memory device to memory device through a common clock input. The clock mode configuration circuit in each memory device is set to a parallel mode for receiving the parallel clock signal, and to a serial mode for receiving a source synchronous clock signal from a prior memory device. Depending on the set operating mode, the data input circuits will be configured for the corresponding data signal format, and the corresponding clock input circuits will be either enabled or disabled. The parallel mode and the serial mode is set by sensing a voltage level of a reference voltage provided to each memory device.

Clock mode determination in a memory system

A clock mode configuration circuit for a memory device is described. A memory system includes any number of memory devices serially connected to each other, where each memory device receives a clock signal. The clock signal can be provided either in parallel to all the memory devices or serially from memory device to memory device through a common clock input. The clock mode configuration circuit in each memory device is set to a parallel mode for receiving the parallel clock signal, and to a serial mode for receiving a source synchronous clock signal from a prior memory device. Depending on the set operating mode, the data input circuits will be configured for the corresponding data signal format, and the corresponding clock input circuits will be either enabled or disabled. The parallel mode and the serial mode is set by sensing a voltage level of a reference voltage provided to each memory device.

A memory device includes core memory such as flash memory for storing data. The memory device includes a first power input to receive a first voltage used to power the flash memory. Additionally, the memory device includes a second power input to receive a second voltage. The memory device includes power management circuitry configured to receive the second voltage and derive one or more internal voltages. The power management circuitry supplies or conveys the internal voltages to the flash memory. The different internal voltages generated by the power management circuitry (e.g., voltage converter circuit) and supplied to the core memory enable operations such as read/program/erase with respect to cells in the core memory.

Non-volatile semiconductor memory having multiple external power supplies

A composite memory device including discrete memory devices and a bridge device for controlling the discrete memory devices. The bridge device has memory organized as banks, where each bank is configured to have a virtual page size that is less than the maximum physical size of the page buffer. Therefore only a segment of data corresponding to the virtual page size stored in the page buffer is transferred to the bank. The virtual page size of the banks is provided in a virtual page size (VPS) configuration command having an ordered structure where the position of VPS data fields containing VPS configuration codes in the command correspond to different banks which are ordered from a least significant bank to a most significant bank. The VPS configuration command is variable in size, and includes only the VPS configuration codes for the highest significant bank being configured and the lower significant banks.

Bridging device having a configurable virtual page size

A method of snap-shot data training to determine the optimum timing of the DQS enable signal in a single read operation is provided. This is accomplished by first writing a Gray code count sequence into the memory and then reading it back in a single burst. The controller samples the read burst at a fixed interval from the time the command was issued to determine the loop-around delay. A simple truth table lookup determines the optimum DQS enable timing for normal reads. Advantageously, during normal read operations, the first positive edge of the enabled DQS signal is used to sample a counter that is enabled every time a command is issued. If the counter sample changes, indicating timing drift has occurred, the DQS enable signal can be adjusted to compensate for the drift and maintain a position centered in the DQS preamble. This technique can also be applied to a system that uses the iterative approach to determining DQS enable timing on power up. Another embodiment of the invention is a simple, low latency clock domain crossing circuit based on the DQS latched sample of the counter.

Synchronous memory read data capture

In an integrated circuit (IC) adapted for use in a stack of interconnected ICs, interrupted through-silicon-vias (TSVs) are provided in addition to uninterrupted TSVs. The interrupted TSVs provide signal paths other than common parallel paths between the ICs of the stack. This permits IC identification schemes and other functionalities to be implemented using TSVs, without requiring angular rotation of alternate ICs of the stack.

Using interrupted through-silicon-vias in integrated circuits adapted for stacking

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Ottawa, Canada

Peter B Gillingham