Unisys Corporation

Sperry Corporation

Unisys Corpoation

Peter B Criswell

Glen R Kregness

Clarence W DeKarske

David R Johnson

John Steven Kuslak

James R McBreen

Merwin H Alferness

David C Johnson

Douglas A Fuller

Wayne D Ward

James Edward Rezek

Thomas D Hartnett

Richard F Paul

Louis B Bushard

Richard M Shelton

Michael J Stella

A system and method for modifying the hardware instruction set of an instruction processor is disclosed. The invention utilizes one or more bits of an instruction opcode and one or more programmable bits stored within the instruction processor to generate a branch address. The branch address is then used to address a storage device such as a microcode RAM to retrieve one or more microcode instructions that control execution of the instruction opcode. Address generation is controlled by selecting a previously unused instruction opcode, then modifying the programmable bits as necessary to generate a desired branch address. By loading modified microcode instructions at the branch address, instruction execution can be modified without changing the hardware design.

System and method for expanding the instruction set of an instruction processor

A system and method for detecting and correcting errors within a control system is disclosed. A storage device stores data values that are used to control one or more circuits within the system. This storage device may operate as a slave, such that the storage device is addressed using address signals provided by an external source. This storage device may also operate as master such that some of the data signals that are read from the storage device are used to generate the address for performing the next reference the storage device. In the former slave scenario, and in some cases wherein the storage device is operating as a master, data signals that would otherwise be employed to generate an address are instead employed as check bits to implement an error detection and correction scheme.

System and method for detecting and correcting errors in a control system

Instruction processor and method supporting dual-mode execution of computer instructions. In various embodiments, certain instructions are executable in one of two modes. The first mode is compatible with the native instruction set and data words, and the second mode is an adaptation suitable for platform independent instructions. A control word RAM is addressed by the operation code of an instruction, and each word in the control word RAM includes an address into a microcode RAM. The address into the microcode RAM is manipulated in accordance with the various embodiments to reference either a first set of microcode for native instructions and data words, or a second set of microcode for execution in a platform-independent mode.

Dual microcode RAM address mode instruction execution using operation code RAM storing control words with alternate address indicator

Apparatus and a method for providing a single instruction that can load a character from memory and perform a character compare. In an illustrative embodiment, this is accomplished by providing indexing apparatus which permits indexing on character boundaries. The characters are loaded from memory, and provided to an ALU unit in a processor, wherein a compare is made with a desired value. The ALU provides a compare result to a jump skip logic block, which notifies the processor whether the instruction immediately following the instruction of the present invention should be skipped or executed.

Testing and string instructions for data stored on memory byte

Method for performing critical path timing analysis on a circuit design having different timing constraints for multiple parallel paths. Method includes clearing the state of the circuit design, setting control lines in the circuit design to a selected set of control signals, and identifying blocking nets of the circuit design to be flagged for timing analysis by simulating the circuit design with the selected set of control signals as input signals. Identified blocking points are added to a list which identifies paths in the circuit design to be analyzed. All possible sets of control signals are processed. Timing analysis is then performed on the circuit design using the list as input data. A critical step is the identification of the blocking points. Blocking points are identified for each net input to a gate in the circuit design having an unknown value, and a known value on an output net from the gate for the selected set of control signals. Blocking points input to the timing analysis tool ensure that these nets are analyzed during critical path timing analysis, so all possible timing violations in the circuit design are detected.

Method of using a four-state simulator for testing integrated circuit

An Internet checksum for use by TCP/IP is generated in a single macro-instruction called a Block Add Octets instruction. Extraneous overhead of macro-instruction looping and bit masking is eliminated by combining checksum operations into a single macro-instruction using a block add approach. The programmer specifies the address in memory and the number of double-words of message data to be added together within a single instance of the Block Add Octets instruction so that looping and jump/branch instructions are not needed. The Block Add Octets instruction fetches all octets (8-bit data segments) contained in full double words from memory and adds them into the checksum. The method handles partial double words of data, full double words, and odd numbers of double words, whereby a double word consists of four octets. The checksum is calculated using one's complement arithmetic rather than two's complement, thereby increasing the speed of checksum calculation because the 'end around carry' is eliminated. The number of octets that can be added to the checksum per processor cycle is greatly increased, thereby significantly improving overall TCP/IP performance.

Method for generating an internet protocol suite checksum in a single

The present invention method is of the type which may be implemented in existing maintenance controllers of large mainframe computers and comprises a method for checking hardware errors which exists in the computing system and are displayable on a display of the type employed to display the state of scan settable latches. The novel method permits a more compact display of the functional operation of the computing system thus permitting a customer engineer to easily identify a faulty latch copy based solely on employing the method and prescribed format. The novel method includes assimilating the state of scannable logic devices such as latches and designators in the computer system and defining functionally the system in which they are located. The binary state of the individual latches are then subdivided into a plurality of one or more groups having the same number of copies and are assigned to a duplicate pseudo having four unique features which define each of the latches in a group. Each of the plurality of groups of latches are converted from their binary form to a code or code group which compacts the binary information and permits deviations of latches within the groups to be more easily detected. Means are provided for detecting errors within groups and for detecting the latch within the group in which the error occurs and for listing the duplicate latches that have failed with associated information which identifies their location.

Method for checking hardware errors

A clock error detection system is provided for a data processing system that employs multiphase clock signals and dual, substantially identical electronic modules. The clock error detection system employs one clock error detection circuit on one module and a second clock error detection circuit on the other electronic module. An error collector is coupled to the first and second clock error detection circuits on both modules to receive the fault signals. Two complementary residue code generators with different moduli are used in each electronic module to generate clock phase error detection signals, which may be used to detect either missing or extra clock phases.

Fault isolation for multiphase clock signals supplied to dual modules

An instruction processor for a data processing system runs arithmetic sequences that are initiated by sequence designator signals and are interrupted by interrupt signals. During operation of the processor logic elements of the processor are selectively cleared by clear signals during time periods that sequence designator signals are in inactive states following the occurrence of an interrupt signal. Dual indentical logic circuits are employed wherein each of the circuits include error circuit elements that are coupled to receive the interrupt signal and arithmetic sequence initiation signals. A comparator is coupled to an output of each of the dual identical logic circuit to receive signals that are used to indicate when an interrupt signal and an arithmetic sequence initiation signal occurs simultaneously in only one of the logic circuits. Clear sequence circuitry in each of the dual identical logic circuits receives the interrupt signal and selectively supplies clear signals to the logic elements.

Method for isolating failures of clear signals in instruction processors

Apparatus for checking and detecting erroneous start signals is provided in the arithmetic section of a high speed instruction processor and may be embodied in other types of processors. The novel logic circuits include circuits for detecting an attempted start signal while a previous instruction is still in process; logic circuits for detecting when an even arithmetic sequence and an odd arithmetic sequence other than the first sequence are being concurrently processed; and logic circuits for detecting when an AR start instruction is being attempted during a wrong minor cycle.

Apparatus and method for checking start signals

Failures of duplicate input signals to two indentical electronic modules which may be units, cards, circuits or other entity, are detected by comparison. In each electronic module functional input signals are captured in a plurality of latches on different, or the same, clock phase. Each input signal is captured directly in latches on the same phase as the functional latch which used it to provide a plurality of link signals which are encoded by techniques, such as parity or residue encoding, and compared. The result of the link signal comparison is stored in a register. The outputs of the register are encoded and are supplied to a comparator which compares a signal from the other identical electronic modules. When miscomparison occurs location of the type of failue is facilitated by the system.

Isolation for failures of input signals supplied to dual modules which

A system for detecting and isolating fault conditions occurring within a digital electronic system. The digital electronic system includes a first digital logic array for generating digital outputs in response to a set of digital signal inputs applied to it. The digital logic array is replicated and the second array is configured to receive the same inputs as the first. The first and second arrays are made to operate in synchrony so as to normally produce identical outputs in the absence of fault conditions occurring either in the first or second array or in the inputs applied to them. The digital outputs from the first array are applied to first and second residue code generators having different modulii. Likewise, the outputs from the second arry are applied to third and fourth residue code generators which are identical in make-up to the first and second residue code generators. The residue codes developed by the first and third generators are applied to a first comparator while the codes developed by the second and fourth generators are applied to a second comparator. The comparator outputs are applied through combinatorial logic so as to provide an output signal indicative of a fault condition when either the first or second comparator produces an output indicative of inequality between respective residue codes.

System for checking duplicate logic using complementary residue codes to

A high speed system utilizing programmably controlled ranks of multiplexers for reformatting data from programmably selected first formats to second formats is described. Interleaved input data is utilized to optimize reformatting rates. The reformatting system provides field selection and justification together with the capability of complementing and magnitude generation of the selected fields. Floating-point operands in two different floating-point formats can be unpacked, that is the characteristic separated from the mantissa and properly aligned, and can be packed by positioning and recombining the characteristic with that associated mantissa. Throughout the entire reformatting process, parity for selected bit groupings is maintained, thereby allowing through checking of reformatting operations. The reformatting system includes programmably selectable constant generation.

Programmable data reformat system

A 72-bit shift matrix, suitable for LSI implementation in gate arrays, is disclosed. Eight byte shifters and eight bit shifters are combined to produce shifts of 0-72 places in either direction, circularly or open ended with zero or sign fill. A means is additionally provided to regenerate original source parity from the matrix outputs for use in thru checking. A single 9-bit parity generator is all that is required to check the correctness of the matrix.

Error checked high speed shift matrix

A method and a means are disclosed for the throughchecking of the normalizer operations of an arithmetic unit of a data processing system involving both integer and floating-point formats in single and double precision operations. A post normalizer is used in conjunction with the main normalizer of the arithmetic unit to determine if the result is indeed normalized. Where the post normalize count is zero, an error designator remains inactivated. However, where the count is non-zero, the error designator is activated to indicate an error exists, unless it is disabled by separate circuitry which detects that the number being shifted is .+-..0.. The preferred embodiment disclosed herein checks the operation of a pair of 72-bit main normalizers with a single 13-bit post normalizer. A plurality of instructions in which this check is significant are illustrated.

Growing community of inventors

Bethel, MN, United States of America

Peter B Criswell