Intel Corporation

Peter B Bloch

David G Ellis

Ali S Oztaskin

Leonard W Cross

Bill A Munson

Balaji Parthasarathy

Louis J Johnson

Gene A Frederiksen

David R Jackson

Steven R Fordyce

Video data is received from multiple video receptors. This multidimensional video data is converted from the video receptors into a multidimensional audio representation of the multidimensional video data and are the multidimensional audio representation is output using multiple audio output devices. The conversion of the multidimensional video data includes generating a three-dimensional representation of the multidimensional video data, and generating an audio landscape representation with three-dimensional features based on the three-dimensional representation.

Three dimensional audio vision

The present invention is directed to a method and apparatus for managing data flow between a serial bus device which operates at a first data rate and a parallel port device which operates at a second data rate. A serial bus receiver receives data from the serial bus device at the first data rate. A buffer unit is coupled to the serial bus receiver and the parallel port device. The buffer unit stores the received data at the first data rate and transfers the stored data to the parallel port device at the second data rate.

Managing data flow between a serial bus device and a parallel port

A method and device is provided for controlling access to a resource by a bus master over a bus coupling the bus master to the resource. The resource includes an intelligent component that controls the operation of the resource. A series of packets is transmitted over the bus between the bus master and the resource, at a transmission speed controlled by the bus master. A request/response logic in the resource controllably throttles transmissions of the packets at the resource, at specified time intervals. Each of the time intervals is set at a time period to assure sufficient time for the intelligent component to complete processing tasks contained in the packets.

Programmable and adaptive resource allocation device and resource use

Briefly, in accordance with one embodiment, an integrated circuit includes: electronic circuitry for transferring digital data signals along a digital data signal path between different clock timing domains. The clock timing domains have a common higher frequency source clock. A first clock timing domain clock signal has a relatively fixed phase and a second clock timing domain clock signal has a relatively varying phase. The electronic circuitry includes delay elements in clock signal paths associated with the digital data signal path so that along the digital data signal path, clock signals in different clock timing domains are respectively staggered for a relatively short time compared with a given cycle of the source clock. The electronic circuitry further includes a digital data signal path including a data value retention element to delay the transfer of digital data signals between different clock timing domains at selected times.

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Portland, OR, United States of America

Peter B Bloch