Arm Limited

Qualcomm Technologies International, Ltd.

Cambridge Silicon Radio Limited

Peter Andrew Rees Williams

Rainer Herberholz

Oded Golombek

Richard Andrew Paterson

Einat Luko

Barnaby Golder

Anthony Lawrence McFarthing

Alexander Klimov

Jonathan Tyson Williams

Nick Jones

Jeffrey Scott Boyer

Narayan Prasad Ramachandran

Sukanta Kishore Panigrahi

Timothy Charles Clapp

Danny Joseph Traynor

Richard Andrew Wilkinson

Jeremy Stark

Peter Collins

Various implementations described herein are related to a device having a first coil-shaped spiral structure for an active shield and a second coil-shaped spiral structure that is wound in-between windings of the first coil-shaped spiral structure. The first coil-shaped spiral structure may provide for a coil-based electro-magnetic (EM) shield as a counter-measure circuit for protecting an underlying circuit.

Active shield structure

Embodiments of the present disclosure advantageously provide a secure boot integrity verification system that is protected against future quantum attacks without relying on correctly functioning hardware security modules (HSMs) for the expected lifetime of the computer system or embedded device.

Secure boot process for a computer system

Disclosed are methods, systems and devices for storing states in a memory in support of applications residing in a trusted execution environment (TEE). In an implementation, one or more memory devices accessible by a memory controller may be shared between and/or among processes in an untrusted execution environment (UEE) and a TEE.

Method, system and circuit for managing a secure memory partition

Disclosed are methods, systems and devices for implementing built-in self-test (BIST) to be performed by an untrusted party and/or in an unsecure testing environment. In an embodiment, a test access port (TAP) on a device may enable a party to initiate execution of one or more BIST procedures on the device. Additionally, such a TAP may enable loading of encrypted instructions to be executed by one or more processors formed on a device under test.

Method and/or system for testing devices in non-secured environment

A monitoring system for monitoring delay of critical path timing margins can include a plurality of adaptive monitoring circuits, where each adaptive monitoring circuit is coupled to a corresponding one of a plurality of paths in a circuit. Each adaptive monitoring circuit can include a first delay element designed to cause a mean timing margin of the plurality of N paths in the circuit to be within one minimum mean unit delay; a second delay element coupled to the first delay element and designed to add a mean delay of k*&#x3c3;; a set-up capture element capturing an output of the second delay element; and a set-up warning comparison element that outputs a set-up warning signal when the output of the set-up capture element and a shadow capture element or a capture element of the corresponding one of the plurality of paths do not satisfy an expected condition.

Delay monitoring scheme for critical path timing margin

A method of operating a voltage regulator including a source voltage rail and a plurality of output voltage rails, the method including: converting a source voltage on the source voltage rail to a respective output voltage on each output voltage rail; selecting an output voltage rail; comparing the output voltage on the selected output voltage rail to a reference voltage for the selected output voltage rail; and if the output voltage of the selected output voltage rail is less than the reference voltage for the selected output voltage rail, controlling the voltage regulator to increase the output voltage on the selected output voltage rail, wherein the frequency at which an output voltage rail is selected is dependent upon the rate at which the voltage regulator has previously increased the output voltage on that output voltage rail.

Voltage regulator

Methods and devices are described, including a near-field communications (NFC) or radio frequency identification (RFID) device comprising an NFC or RFID circuit, an antenna having at least a first terminal, a first rectifier connected to the first terminal of the antenna, a switch between the first rectifier and the NFC or RFID circuit, a voltage detector for detecting a voltage in the device caused by a signal received at the antenna, and a control module for controlling the switch, wherein when the voltage exceeds a threshold magnitude, the control module controls the switch to be in an open state and, after a predetermined time period, determines whether the voltage still exceeds the threshold magnitude and, if the voltage still exceeds the predetermined magnitude, controls the switch to be in the open state.

Protection of an NFC or RFID radio in the presence of strong electromagnetic fields

An integrated circuit having an external connection pad and an active circuit for generating signals to be output from the integrated circuit by means of the pad, the integrated circuit including an interface circuit associated with the pad, the interface circuit including a latch coupled between the pad and an output of the active circuit, the latch being capable of operating in a first mode in which the state of the pad follows the state of the output of the active circuit and a second mode in which the state of the pad is held by the latch.

Integrated circuit operating active circuitry and chip pads in different operating modes and at different voltage levels

A communication device comprising: a first radio capable of communicating according to a first protocol and having a set of operational modes; and a second radio capable of communicating according to a second protocol, the communication device being configured to, in dependence on one or more communications by the second radio in accordance with the second protocol, selecting one mode of operation for the first radio from the set of operational modes, wherein said one or more communications comprises: sending a first message; and a response or non-response to the first message.

Power saving for a communication device

A method of controlling an integrated circuit chip including first and second clock sources, the first clock source being more thermally stable and having a higher power consumption, the integrated circuit chip being operable in a first mode in which the first clock source is inactive and the second clock source active and in a second mode in which the first and second clock sources are active, the method including operating the integrated circuit chip in the first mode; taking a measurement indicative of temperature; if the measurement indicates that the temperature is outside of a temperature band: activating the first clock source so as to operate the integrated circuit chip in the second mode; recalibrating the second clock source against the first clock source; and following the recalibration, deactivating the first clock source so as to return the integrated circuit chip to the first mode.

Growing community of inventors

Cambridge, United Kingdom

Peter Andrew Rees Williams