Minnesota Mining and Manufacturing Company

Peter Amass

Robert S Bradford

A circuit is disclosed for serially formatting digital information such as may be provided in a digital audio magnetic tape recorder in a succession of data blocks or frames, each containing the same number of digital bits and in which each frame is delineated by a uniquely occurring digital frame synchronizing signal. The digital information is formatted in a Miller or 3F code in which allowable transitions between successive '1's and '0's result in pulses which are 1, 1-1/2 or 2 times the duration of a bit cell, hence giving rise to three characteristic frequencies and the term 3F code. The frame synchronizing signal is generated by providing a signal comprising digital bits 1-0-0-1, which signal in a 3F code is characterized by a transition between the adjacent '0's, and by appropriately inhibiting that transition, thus creating a pulse which is three times the duration of a unit cell, hence giving rise to a new fourth frequency which cannot be normally created by any succession of '1's or '0's.

Digital frame synchronizing circuit

A video compensation network is disclosed in which the pedestal level and the peak white level of a composite video signal are automatically maintained within predetermined limits. The network includes two digital/feedback loops for independently detecting and generating correction signals which are used to control the respective pedestal and peak white levels. The feedback loops are activated to make incremental adjustments to the two levels once per video field.

Growing community of inventors

Camarillo, CA, United States of America

Peter Amass