United Silicon Carbide, Inc.

Peter Alexandrov

Anup Bhalla

Trench JFETs may be created by etching trenches into the topside of a substrate of a first doping type to form mesas. The substrate is made up of a backside drain layer, a middle drift layer, and topside source layer. The etching goes through the source layer and partly into the drift layer. Gate regions are formed on the sides and bottoms of the trenches using doping of a second type. Vertical channel regions are formed behind the vertical gate segments via angled implantation using a doping of the first kind, providing improved threshold voltage control. Optionally the substrate may include a lightly doped channel layer between the drift and source layers, such that the mesas include a lightly doped channel region that more strongly contrasts with the implanted vertical channel regions.

Trench vertical JFET with improved threshold voltage control

A shielded junction field effect transistor (JFET) is described having gate trenches and shield trenches, the shield trenches being deeper and narrower than the gate trenches. The gate trenches may be fully aligned, partially aligned, or separated from the shield trenches.

Trench shield connected JFET

The present disclosure describes structures and processes to produce high voltage JFETs in wide-bandgap materials, most particularly in Silicon Carbide. The present disclosure also provides for products produced by the methods of the present disclosure and for apparatuses used to perform the methods of the present disclosure.

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Lawrence, NJ, United States of America

Peter Alexandrov