Teradyne, Inc.

Peter A Reichert

Benjamin J Brown

Joseph Francis Wrinn

Michael W Hamblin

Govindarajan T Srinivasan

George W Conner

Craig Robertson

Chris Reed

Valquirio Nazare Carvalho

Robert Bruce Gage

Bradford B Robbins

Shant Orchanian

Thien D Nguyen

Bill Sopkin

Dennis R LaFosse

Brian J Arkin

David M Proudfoot

An example test system includes a test carrier to receive a device to test. The test carrier includes test components to perform at least a structural test on the device. The example test system also includes a slot to receive the test carrier. The slot includes an interface to which the test carrier connects to enable the test carrier to communicate with a system that is part of the test system or external to the test system.

System for testing devices inside of carriers

According to one embodiment, a method for processing one or more X-ray images includes: receiving at least one image of the one or more X-ray images, the one or more X-ray images being of an assembly extending along a plane; based on the at least one image, autonomously determining a respective displacement value for each of portions of the assembly with respect to one or more directions of the plane, each of the displacement values being determined relative to a respective actual value; storing the displacement values; and applying a rule to the stored displacement values, the rule being for determining a defect status of the assembly.

X-ray inspection of solder reflow in high-density printed circuit board applications

According to one embodiment, a calibration system for calibrating image data produced by an imaging system is provided. The calibration system includes a processor configured for: receiving the image data from the imaging system; receiving a plurality of reference values from the imaging system; and calibrating the image data using the reference values. The reference values correspond to air image data produced by the imaging system.

Method of and system for calibration of inspection systems producing X-ray images

A test system with multiple instruments. Some instruments act as controller instruments and others act as controlled instruments. Each instrument includes a clock generator that synthesizes one or more local clocks from a reference clock. The reference clock is a relatively low frequency clock that can be inexpensively but accurately generated and distributed to all of the instruments. A communication link between instruments is provided. Timing circuits within instruments that are to exchange time information are synchronized to establish a common time reference. Thereafter, instruments communicate time dependent commands or status messages asynchronously over the communication link by appending to each message a time stamp reflecting a time expressed relative to the common time reference. The test system includes digital instruments that contain pattern generators that send command messages to analog instruments, which need not include pattern generators. The architecture simplifies design of analog instruments and avoids redesign of analog instrument as pattern rates of digital instruments change.

Instrument with interface for synchronization in automatic test equipment

Data can be processed in automatic test equipment by dividing the test sites into groups and processing each group using a corresponding processor in a group of processors. Sections of the test equipment can communicate via a tester bus to a particularly designed multi-stream switch. The multi-stream switch can communicates with a plurality of processors via a plurality of processor busses. Each of the processors can run a separate instance of test software without interfering with software running on any other of the processors. The inventive protocol can be embodied essentially in hardware that can be adapted to an existing infrastructure without requiring substantial modifications of existing hardware or software.

Multi-stream interface for parallel test processing

According to one embodiment, a system for linearizing image data corresponding to one or more objects and output by an imaging device is provided. The system includes a processor configured for: receiving the image data from the imaging device; and producing a generally linear relationship between the image data and a thickness of the one or more objects. The generally linear relationship is produced according to the equation I is an intensity of the image data, Iis an intensity of energy produced by the imaging device for outputting the image data, &#x3bc; is an attenuation coefficient of the one or more objects, and l is the thickness of the one or more objects.

Method of and system for obtaining linear data for object scanned using non-collimated, poly-energetic X-rays

Automatic test system with synchronized instruments

A numeric counter oscillator is disclosed comprising a quotient accumulator and a remainder accumulator. The quotient accumulator has a programmable input for receiving a QUOTIENT value, a reference clock input and a multi-bit output. The output is adapted for transmitting an output value OUT representing an accumulated quotient sum. The multi-bit output increments by a predetermined amount in response to each reference clock period. The remainder accumulator comprises programmable inputs for receiving respective REMAINDER and DIVISOR values, a a reference clock input and a multi-bit output representing an accumulated digital remainder sum less than a predefined digital integer. The remainder accumulator further comprises a comparator having a first input for receiving a programmed divisor value, and a second input for receiving the remainder accumulator multi-bit output. The comparator is operative to generate an increment carry signal for application to the quotient accumulator when the remainder multi-bit output reaches the predefined integer value.

Multi-stage numeric counter oscillator

A clock system is disclosed for distributing and generating a digital clock signal for a plurality of electronic assemblies. The clock system includes a remote fixed-frequency clock for generating a first clock signal of a first frequency and a plurality of local clock modules. The local clock modules are respectively disposed on the plurality of electronic assemblies and each include synthesizer circuitry for creating a variable clock signal of a different frequency than the first frequency. Fanout circuitry is coupled between the remote fixed frequency clock and the plurality of local clock modules to distribute the first clock signal.

Clock architecture for a frequency-based tester

A timing system is disclosed that responds to pattern generation circuitry for producing test patterns for application to a device-under-test. The timing system includes a timing memory circuit that stores programmed edge timings for the patterns and couples to timing logic including a master oscillator and a plurality of fixed edge generators. The fixed edge generators are responsive to the programmed edge timings to produce the event timing signals.

Low cost timing system for highly accurate multi-modal semiconductor testing

An automatic test system useful for testing source synchronous devices at high speed. The data outputs of the device under test are routed to channel circuitry within the test system through coaxial cables. The test system includes a buffer amplifier on a device interface board to fan out the DATA CLOCK generated by the device under test to that channel circuitry. The interconnection between the buffer amplifier and the channel circuitry is provided through a coax with low dielectric constant, to compensate for the delay introduced by the buffer amplifier.

Method and apparatus for testing integrated circuit chips that output clocks for timing

A pattern generator for use in a memory tester to provide packet address and data signals to a packet-based memory-under-test is disclosed. The pattern generator includes an address source for generating an external packet memory address signal. The external packet memory address signal represents a plurality of addressable memory elements in the memory-under-test. A plurality of data generators are disposed in parallel relationship and coupled to the output of the address source to receive at least a portion of the packet memory address signal. Each of the data generators has logic operative to derive an internal address from the packet address. The internal address corresponds to an individual memory element within the memory under test. A sequencer is disposed at the outputs of the data generators to distribute the data generator outputs in a packet waveform for application to the memory-under-test.

Pattern generator for a packet-based memory tester

A tester having a fast but flexible pattern generator which is implemented using readily available memories. The tester includes a pattern memory which holds test vectors. The vectors are organized into modules. The order of execution of the modules is selected from a list stored in memory. In the preferred embodiment, memories which operate in burst mode are used to implement the pattern memory. To compensate for the decrease in data rate which occurs when execution switches between modules in the middle of a burst, the memory refresh rate is dynamically altered upon switching between modules.

Memory architecture for automatic test equipment using vector module table

Fast loading of a vector test pattern in a semiconductor device tester. Fast loading is achieved through the use of delta coding of vectors in conjunction with a vector cache in the vector loading circuitry of the tester. In this way, the total amount of information transmitted during the loading operation is reduced. Hardware required to implement the method is minimized by using random access memory conventionally found in automatic test equipment for the vector cache.

Growing community of inventors

Thousand Oaks, CA, United States of America

Peter A Reichert