Sun Microsystems, Inc.

Peter A Mehring

Robert D Becker

Herbert Lopez-Aguado

Curtis R Priem

Michael G Lavelle

Satyanarayana Nishtala

Daniel E Lenoski

Thomas P Webber

Guy Moffat

Varoujan Garapetian

Cau L Nguyen

Christopher R Owen

A computer system with a multiplexed address bus that is shared by both system memory and by slave devices is described. The slave devices are incorporated into an existing system memory configuration by providing a bus controller to execute a two-cycle address sequence on the multiplexed address bus. The address sequence is followed by a transfer of data. A random latency can exist between the time of receiving address information and the time of receiving data corresponding to the address information. This random latency can be exploited by the system CPU for other computational purposes. The bus controller of the system executes multiple, or pipelined, data writes to the bus before an acknowledgement for the first data write is received. In this scheme, the acknowledgement for the first data write is typically sent during the same time period that the subsequent data writes are being received. Consequently, data transfer acknowledgements overlap data writes. This overlapping operation allows the bus to be completely utilized during write operations, thereby improving data bandwidth.

Computer system with a shared address bus and pipelined write operations

The system of the present invention includes programmable logic to generate watchpoint traps which cause a branch to determined trap code and breakpoint signals which cause the stopping of the system dock. Furthermore, the system can measure system performance criteria. The logic is flexible and easy to program, but sophisticated in application to provide a variety of criteria that trigger on events which in turn increment the counters. In the preferred embodiment, the system includes two counters and trigger decode logic to increment the counters. Each counter is independently programmable to enable the user to determine such performance information as average latency, which is a combination of one counter counting the number of occurrences of a particular event and a second counter counting the duration of the events. Both counters can be programmed to measure on edges or levels of signals. In addition, the triggers can be used in a cascaded structure, wherein the first counter is used to generate a trigger which may be further qualified by the second counter. Using this implementation, a more flexible counting strategy is provided. Furthermore, by using the two counters in a cascaded fashion, the occurrence on one type of event can be used to monitor the occurrence of a second type of event in order to determine the occurrence of a combination of events. In addition, both watchpoint traps and breakpoint signals can be generated based upon the occurrence of a variety of events internal to the component and not easily accessible during execution by the user.

Method and apparatus for performing on-chip measurement on a component

A system and method for performing conditionally cache allocate operations to a data cache in a computer system. As supervisor mode operations typically do not experience data locality of accesses frequently found in user mode operations, it has been determined that performance benefits can be achieved by inhibiting cache allocate operations during supervisor mode. When a write miss to the cache occurs, the memory management unit checks the state of the processor status register to determine the mode of the processor. If the processor status register indicates that the processor is in supervisor mode, the memory management unit issues a signal to the data cache controller that the data is non-cacheable. When the data cache controller receives a non-cacheable signal, the cache allocate process is not performed. The non-cacheable signal is issued by the memory management unit while the processor is in supervisor mode regardless of the state of the cacheable status bit associated with the memory. Thus, if the processor is not in supervisor mode, the memory management unit will issue a non-cacheable signal to-the data cache controller based upon the state of the cacheable status bit associated with the memory. This status bit is typically found in the corresponding page table entry in the page table of a translation look aside buffer. Therefore, although a supervisor mode operation inhibits a cache allocate operation, subsequent non-supervisor mode operations to the same data will proceed based upon the state of the cacheable status bit associated with the memory.

Method and apparatus for optimizing supervisor mode store operations in

A method and apparatus for the pipelining of data during direct memory accesses. The processor includes an external bus controller, which receives data transmitted across the external bus from an external device, and forwards the data onto the memory bus for transfer to the memory. Similarly, the bus controller receives data to be written to external device from the memory and transfers it across the external bus to the external device. The bus controller includes logic to detect burst transfers and word alignment to determine the minimum number of words that can be transferred across the memory bus while the data transfer from the external device is ongoing. Therefore, instead of waiting for the entire block of data to be received into the processor before transferring it to the memory, portions of the block transferred, for example, two words at a time, are transferred to the memory, while additional data is being received at the processor. If two words are transferred at a time across the memory bus, then at the end of a block transfer only one additional cycle is required to transfer the last two words of data to the memory. Similarly, for a write operation to the external device, data can be piecewise transferred across the slower external bus as it is received in the bus controller in order to minimize the time required to complete the transfer.

Method and apparatus for the pipelining of data during direct memory

A translation look aside buffer including virtual page table pointer tags provides a system and method for accessing page table entries in page memory of the translation look aside buffer with decrease latencies caused by accesses to increasing levels of page tables during a table walk of the page table. Virtual tags identifying page table pointers at a predetermined level of the page table higher than the initial context level of the page table are included in the tag memory of the translation look aside buffer. These virtual tags provide a pointer which directly points to the page table pointer at that predetermined level of the page table. Therefore, if a TLB miss occurs wherein a tag for a page table entry corresponding to the virtual address is not found, a comparison is performed to determined if a corresponding virtual tag PTP is located in the tag memory. If the corresponding virtual tag PTP is found in the tag memory, access is gained to the PTP in the page table without the need for performing a time consuming table walk through the lower levels of the page table.

Method and apparatus for the reduction of tablewalk latencies in a

A translation lookaside buffer for use with a virtual memory system including apparatus for storing virtual addresses, apparatus for storing a physical address associated with each of the virtual addresses, some of the physical addresses corresponding to pages in which the information sought by the virtual address resides, and others of the physical addresses corresponding to pages in which the physical address of information sought by the virtual address resides.

Translation lookaside buffer apparatus and method with input/output

A translation lookaside buffer for caching virtual addresses from a plurality of sources along with the associated physical addresses which physical addresses must be rapidly accessable and in which virtual addresses may appear simultaneously from two of the sources requiring translation into physical addresses, including a primary cache for storing a plurality of individual virtual addresses and associated physical addresses from all of the plurality of sources, apparatus for storing a single virtual address and its associated physical address from one of the plurality of sources which occurs most often each time a virtual address and an associated physical address from that one of the plurality of sources is referenced in the primary cache, and apparatus for ascertaining whether the virtual address held in the apparatus for storing a single virtual address and an associated physical address is a virtual address sought when an attempt is made to access the primary cache for a virtual address from the one of the plurality of sources and for another of the plurality of sources simultaneously.

Apparatus for increasing the number of hits in a translation lookaside

In the memory access unit of the present invention, the memory request logic is centralized in the memory management unit (MMU). The MMU instructs the MCU, which interfaces directly with the DRAMs, on the type of memory access to perform. By centralizing the memory requests, the MMU is able to maintain an account of each memory access, thereby providing the MMU the means to determine if a memory access fulfills the requirements of a fast page mode access before a request is made to the MCU. The MMU comprises the row address comparator which can execute the row address comparison in parallel with the cache lookup. Therefore, if the cache lookup determines a memory access is required, a specific fast page mode memory access request can be made, without the memory controller incurring the additional delay of checking the row address. Thus, by using the memory access unit of the present invention, the system can default to fast page mode access without the additional penalty normally incurred by comparing the row address in a serial manner.

Method and apparatus for increasing the speed of memory access in a

A method and apparatus for saving memory space in a buffer whereby the valid bit in the entry of the translation lookaside buffer for a cache memory is collapsed into one of the level bits indicating the length of the virtual address. During the lookup of the translation lookaside buffer, the virtual address in each entry is compared with the virtual address from the CPU if the level/valid bit is set, i.e. the entry is valid. If the level/valid bit is not set, then no compare takes place and the lookup continues to the next entry. The length of the virtual address to be compared is further determined by the status of the remaining level bits.

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Sunnyvale, CA, United States of America

Peter A Mehring