Maxtor Corporation

Quantum Corporation

Peter A McEwen

Kelly K Fitzpatrick

Ara Patapoutian

Ke Han

Bahjat Zafer

Eduardo Gentile Veiga

Bahjat Zafar

Murat Erkocevic

James Fitzpatrick

Bruce Douglas Buch

Jeffrey Lee Sonntag

Kevin Dean Fisher

Michael D Leis

Ba-Zhong Shen

Patrick J Moran

Bill Richard Baker

Stan Shepherd

Tim Everett

Steve Aronson

Hossein Sedarat

Jennifer Stander

Mike Moser

A two-stage sampling data detector for a partial response channel having a channel code encoder for encoding user information sequences into blocks of code words in accordance with a predetermined channel block code characterized by a list of most likely error-events comprising impermissible code words. The detector includes a first-stage detector, such as a Viterbi detector, connected to receive samples from the partial response channel and matched to characteristics of the channel and not to the channel code, puts out unchecked bit estimates. A second stage post-processor checks the bit estimates in relation to derived detector decision metrics information and the channel block code, and puts out post-processed bit estimates to a channel code decoder after correcting detected erroneous sequences in accordance with the decision metrics information, information derived from the channel code, and the list of most likely error-events. A method for generating the channel block code is also described.

Two stage detector having viterbi detector matched to a channel and post processor matched to a channel code

The invention is a modulation system that encodes symbols in accordance with a modulation code which, for a given communications channel, produces a signal that at the decoder includes maximized sample timing information in each encoded symbol. For systems that use PLLs to control a sample timing clock, the sample timing information is the average or squared slope. The modulation code used for a given system is selected based on the target response h(x) of the associated communications channel, such that h (x)*rexceeds a predetermined threshold value, where '*' represents convolution and ris a modulation code symbol. To reduce the bit overhead, or code rate, the inventive modulation system provides more modulation code symbols at the start of a data block, or sector, when system jitter is expected to be relatively high in response, for example, to the movement of a read head. The system then includes fewer modulation code symbols later in the block, when the system jitter associated with a read or receive operation is reduced. The system thus provides sufficient timing information to minimize PLL jitter.

Method and apparatus for utilizing modulation codes that produce maximized sample timing information

Determining a phase error in a data signal includes detecting bits in an original data signal, determining a phase error in the original data signal based on the detected bits, adjusting a clock signal based on the phase error, sampling the original data signal with the clock signal to produce a sampled data signal, and repeating detecting, determining, adjusting and sampling using the sampled data signal instead of the original data signal.

Determining the timing of a data signal

A method and system for self-servo writing a disk drive by transferring a servo reference pattern by magnetic printing onto at least one storage surface of a reference disk, wherein a resulting printed reference pattern includes embedded servo information providing servo timing and transducer head position information; assembling the disk drive including the steps of installing at least said disk into the disk drive and enclosing said disk and the data transducers within a housing sealed against particulate contamination from an eternal ambient environment; reading the printed reference pattern from said disk via at least one transducer head to generate a readback signal; sampling the readback signal at a sampling rate to generate a sampled signal; processing the sampled signal waveform specturm to generate a recovered signal including the embedded servo information and a fundamental frequency of the sampled signal; using the servo information from the recovered signal to precisely position and maintain the data transducers at concentric track locations of disk storage surfaces; and self-writing disk drive servo patterns onto the storage surfaces at the concentric track locations with the data transducers in accordance with disk drive servo pattern features.

Self-writing of servo patterns in disk drives

Adjusting a clock signal includes receiving a data stream, detecting a bit in the data stream using a first amount of data in the data stream, adjusting the clock signal based on the detected bit, detecting the bit in the data stream using a second amount of data in the data stream, the second amount of data comprising more data than the first amount of data, and correcting the clock signal if a result of initial detecting differs from a result of subsequent detecting.

System and method for clock adjustment by subsequently detecting a target bit of data stream, re-adjusting, and correcting clock based on difference in detected bit

A parity check matrix is generated for detecting predefined errors in a coded string of bits. A column of the matrix is generated by selecting values for elements in the column and processing a predefined error with the selected values in order to produce a syndrome. The selected values are assigned to the column of the parity check matrix if an element of the syndrome has a value indicative of the predefined error.

Detecting errors in coded bit strings

Sampling data with wide bi-phase code symbols includes sampling a wide bi-phase code symbol in the data a number (N) of times to produce samples of data, selecting a subset of the samples, determining which sample in the subset of samples has a largest magnitude, and selecting a subset of samples in a subsequent wide bi-phase code symbol based on a sample in a previous subset that has the largest magnitude.

Asynchronously sampling wide bi-phase codes

A scheme (apparatus and methods) for recovering encoded data from a data signal representing one or more data symbols and subject to random errors and transient errors. A system in accordance with this scheme includes a transient error detector, a reliability detector, an erasure flagger, and a decoder. The transient error detector is coupled to receive the data signal and is configured to identify one or more characteristics (e.g., a starting location and a midpoint location) of a transient error (e.g., a TA) in the data signal. The reliability detector is configured to compute a reliability metric for each data symbol. The erasure flagger identifies erasures based upon signals received from the transient error detector and the reliability detector. The decoder is configured to treat a data symbol as an erasure or as a valid data symbol based upon the output of the erasure flagger.

Reading encoded information subject to random and transient errors

A methodology for designing an implementing high rate RLL codes is optimized for application to 10-bit ECC symbols, and provides rate 20/21, rate 50/51, rate 90/91 and other modulation code rates for use in magnetic recording channels. A relatively small subcode encoding&mdash;one easy to implement&mdash;is applied to a portion of the input stream, and the resulting base codeword is partitioned into nibbles that, in turn, are interleaved among the unencoded ECC symbols. Code constraints on the subcode word nibbles depend upon the values of adjacent unencoded symbols. The resulting codes provide excellent density and error propagation performance.

High rate runlength limited codes for 10-bit ECC symbols

A method reducing data format overhead in a storage device. A sequence detector includes a series of states and a path memory of predetermined length. This method includes steps of writing a predetermined shortened pad pattern at the end of a user data field pattern to a signal-degrading storage medium such as magnetic tape or disk; generating samples during read back of the user data field pattern and the shortened pattern; and, controlling the sequence detector during receipt of pad samples to converge at only one or several predetermined detector states during a convergence sequence. The convergence sequence, and the detector pad are shorter than a sequence needed to traverse the entire length of the path memory. The final state reached during the sequence can be used to provide an accurate estimate of a last user data bit of the user data field pattern.

Method for reducing data overhead in PRML data channel

A discrete-time filtering method for identifying defects in a magnetic medium, comprising the steps of: reading data signals from at least a portion of the medium; sampling the data signals to generate discrete time sample data; processing the sample data in a discrete time filter to detect deviation of the signal corresponding to media defects; and comparing the deviation of the signal to one or more threshold values to identify corresponding defect types on the recording medium. The filter can be configured to have an impulse response substantially matched to deviation of the signal corresponding to media defects.

Method and system for detection recording media defacts

A methodology for designing and implementing high rate RLL codes is optimized for application to 10-bit ECC symbols, and provides rate 30/31, rate 40/41, rate 50/51 and much higher modulation code rates for use in magnetic recording channels. A relatively small subcode encoding&mdash;one easy to implement&mdash;is applied to a portion of the input stream, and the resulting base codeword is partitioned into nibbles that, in turn, are interleaved among the unencoded ECC symbols. Code constraints on the subcode word nibbles depend upon the values of adjacent unencoded symbols. The resulting codes provide excellent density and error propagation performance.

A methodology for designing and implementing high rate RLL codes is optimized for application to 8-bit ECC symbols, and provides modulation code rates including rate 32/33; rate 48/49; rate 56/57; rate 72/73; rate 80/81 and other code rates for use in magnetic recording channels. A relatively small subcode encoding&mdash;one easy to implement&mdash;is applied to a portion of the input stream, and the resulting base codeword is partitioned into nibbles that, in turn, are interleaved among the unencoded ECC symbols. Code constraints on the subcode word nibbles depend upon the values of adjacent unencoded symbols. The resulting codes provide excellent density and error propagation performance.

High rate runlength limited codes for 8-bit ECC symbols

A method and apparatus for encoding a sequence of 32 bit digital data words into a sequence of 33 bit code words in consonance with predetermined minimum zero run length (d) and predetermined maximum zero run length (k) for recording upon a magnetic medium within a magnetic recording channel is disclosed. The method comprises steps of dividing each data word into eight data nibbles, determining whether any data nibble contains all zeros. If no code violation, mapping the eight data nibbles to seven code nibbles and to four bits of a five bit code sub-word and setting a fifth control bit to one. If one or more code violations are present, embedding code violation locations within at least the five bit code sub-word and other code nibbles if necessary and remapping data nibbles ordinarily directed to the code sub-word and nibble locations to code locations otherwise containing the data nibbles determined to be code violations.

Growing community of inventors

Santa Clara, CA, United States of America

Peter A McEwen