Apple Inc.

Peter A Lisherness

Lior Zimet

Richard F Russo

Gaurav Garg

James Vash

Jeff Gonion

Jeonghee Shin

Amir Kleen

Sebastian Werner

Techniques are disclosed relating to performing remote invalidation of memory access permission information. In some embodiments, primary processor circuitry is configured to, based on execution of a remote permission table invalidate instruction (e.g., an ISA-defined instruction), send a remote invalidate command to secondary processor circuitry. The secondary processor circuitry includes secondary processor permission circuitry and is configured to, in response to the remote invalidate command sent by the primary processor, invalidate one or more entries in the secondary processor permission circuitry. In some embodiments, the secondary processor performs the invalidate without executing any instructions on the secondary processor circuitry.

Invalidation of permission information stored by another processor

A configurable computer system is disclosed. The computer system includes a set of processing blocks and a set of programmable registers. A given one of the programmable registers corresponds to at least one of the processing blocks. The computer system is configured to receive a harvesting command that writes a disable value to a group of the programmable registers corresponding to a group of the set of processing blocks to be disabled for a selected computing platform of a plurality of different computing platforms. One or more hardware circuits are configured to perform tasks after a given boot of the computer system, the more tasks utilizing circuitry in the group of the set of processing blocks. A power control circuit is configured to, after tasks have been performed, temporarily disable the group of the set of processing blocks, thereby configuring the computer system for the selected computing platform.

Functional circuit block harvesting in computer systems

An apparatus includes a communication bus circuit, a memory circuit, a queue manager circuit, and an arbitration circuit. The communication bus circuit includes a command bus and a data bus separate from the command bus. The queue manager circuit may be configured to receive a first memory request and a second memory request, each request including a respective address value to be sent via the command bus. The first memory request may include a corresponding data operand to be sent via the data bus. The queue manager circuit may also be configured to distribute the first memory request and the second memory request among a plurality of bus queues. Distribution of the first and second memory requests may be based on the respective address values. The arbitration circuit may be configured to select a particular memory request from a particular one of the plurality of bus queues.

Arbitration sub-queues for a memory circuit

An integrated circuit (IC) configurable for use in one of a number of possible platforms is disclosed. The IC includes a number of different functional circuit blocks and a plurality of programmable register. The programmable registers, when programmed, can cause corresponding functional circuit blocks to be fully or partially disabled. The different platforms support different sets of peripherals. The IC is thus configured, using the programmable registers, for use in a particular platform to support its corresponding set of peripherals, while another instance of the IC may be configured for use in another platform, supporting its particular set of peripherals.

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Los Gatos, CA, United States of America

Peter A Lisherness