Micron Technology Incorporated

Aptina Imaging Corporation

Round Rock Research, LLC

Peter A Benson

Charles Martin Watkins

Salman Akram

Warren M Farnworth

Alan G Wood

David R Hembree

Kyle K Kirby

William Mark Hiatt

Sidney B Rigg

James M Wark

Pary Baluswamy

The following disclosure describes several embodiments of (1) methods for wafer-level packaging of microelectronic imagers, (2) methods of forming electrically conductive interconnects in microelectronic imagers, (3) methods for forming optical devices for microelectronic imagers, and (4) microelectronic imagers that have been packaged using wafer-level packaging processes. Wafer-level packaging of microelectronic imagers is expected to significantly enhance the efficiency of manufacturing microelectronic imagers because a plurality of imagers can be packaged simultaneously using highly accurate and efficient processes developed for packaging semiconductor devices. Moreover, wafer-level packaging of microelectronic imagers is expected to enhance the quality and performance of such imagers because the semiconductor fabrication processes can reliably align an optical device with an image sensor and space the optical device apart from the image sensor by a desired distance with a higher degree of precision.

Wafer-level packaged microelectronic imagers having interconnects formed through terminals

A method for removing the edge bead from a substrate by applying an impinging stream of a medium that is not a solvent for the material to be removed. The medium is applied to the periphery of the substrate with sufficient force to remove the material. Also, an apparatus to perform the inventive method.

Non-chemical, non-optical edge bead removal process

A method for removing the edge bead from a substrate by applying an impinging stream of a medium that is not a solvent for the material to be removed. The medium is applied to the periphery of the substrate with sufficient force to remove the material. Also an apparatus to perform the inventive method.

Low temperature processed back side redistribution lines (RDLs) are disclosed. Low temperature processed back side RDLs may be electrically connected to the active surface devices of a semiconductor substrate using through wafer interconnects (TWIs). The TWIs may be formed prior to forming the RDLs, after forming the RDLs, or substantially simultaneously to forming the RDLs. The material for the back side RDLs and various other associated materials, such as dielectrics and conductive via filler materials, are processed at temperatures sufficiently low so as to not damage the semiconductor devices or associated components contained on the active surface of the semiconductor substrate. The low temperature processed back side RDLs of the present invention may be employed with optically interactive semiconductor devices and semiconductor memory devices, among many others. Semiconductor devices employing the RDLs of the present invention may be stacked and electrically connected theretogether.

Semiconductor devices and assemblies including back side redistribution layers in association with through wafer interconnects

A support structure for use with a semiconductor substrate in thinning, or backgrinding, thereof, as well as during post-thinning processing of the semiconductor substrate includes a portion that extends substantially along and around an outer periphery of the semiconductor substrate to impart the thinned semiconductor substrate with rigidity. The support structure may be configured as a ring or as a member that substantially covers an active surface of the semiconductor substrate and forms a protective structure over each semiconductor device carried by the active surface.

Support structure for use in thinning semiconductor substrates and for supporting thinned semiconductor substrates

Microelectronic devices, methods for packaging microelectronic devices, and methods for forming vias and conductive interconnects in microfeature workpieces and dies are disclosed herein. In one embodiment, a method includes forming a bond-pad on a die having an integrated circuit, the bond-pad being electrically coupled to the integrated circuit. A conductive line is then formed on the die, the conductive line having a first end portion attached to the bond-pad and a second end portion spaced apart from the bond-pad. The method can further include forming a via or passage through the die, the bond-pad, and the first end portion of the conductive line, and depositing an electrically conductive material in at least a portion of the passage to form a conductive interconnect extending at least generally through the microelectronic device.

Microelectronics devices, having vias, and packaged microelectronic devices having vias

A support structure for use with a semiconductor substrate in thinning, or backgrinding, thereof, as well as during post-thinning processing of the semiconductor substrate includes a portion which extends substantially along and around an outer periphery of the semiconductor substrate to impart the thinned semiconductor substrate with rigidity. The support structure may be configured as a ring or as a member which substantially covers an active surface of the semiconductor substrate and forms a protective structure over each semiconductor device carried by the active surface. Assemblies that include the support structure and a semiconductor substrate are also within the scope of the present invention, as are methods for forming the support structures and thinning and post-thinning processes that include use of the support structures.

Methods for thinning semiconductor substrates that employ support structures formed on the substrates

Microelectronic imager assemblies comprising a workpiece including a substrate and a plurality of imaging dies on and/or in the substrate. The substrate includes a front side and a back side, and the imaging dies comprise imaging sensors at the front side of the substrate and external contacts operatively coupled to the image sensors. The microelectronic imager assembly further comprises optics supports superimposed relative to the imaging dies. The optics supports can be directly on the substrate or on a cover over the substrate. Individual optics supports can have (a) an opening aligned with one of the image sensors, and (b) a bearing element at a reference distance from the image sensor. The microelectronic imager assembly can further include optical devices mounted or otherwise carried by the optics supports.

Microelectronic imagers with optical devices and methods of manufacturing such microelectronic imagers

A method for forming at least one conductive element is disclosed. Particularly, a semiconductor substrate, including a plurality of semiconductor dice thereon, may be provided and a dielectric layer may be formed thereover. At least one depression may be laser ablated in the dielectric layer and an electrically conductive material may be deposited thereinto. Also, a method for assembling a semiconductor die having a plurality of bond pads and a dielectric layer formed thereover to a carrier substrate having a plurality of terminal pads is disclosed. At least one depression may be laser ablated into the dielectric layer and a conductive material may be deposited thereinto for electrical communication between the semiconductor die and the carrier substrate. The semiconductor die may be affixed to the carrier substrate and at least one of the dielectric layer and the conductive material may remain substantially solid during affixation therebetween. The methods may be implemented at the wafer level.

Method for creating electrically conductive elements for semiconductor device structures using laser ablation processes and methods of fabricating semiconductor device assemblies

An elevated containment structure in the shape of a wafer edge ring surrounding a surface of a semiconductor wafer is disclosed, as well as methods of forming and using such a structure. In one embodiment, a wafer edge ring is formed using a stereolithography (STL) process. In another embodiment, a wafer edge ring is formed with a spin coating apparatus provided with a wafer edge exposure (WEE) system. In further embodiments, a wafer edge ring is used to contain a liquid over a wafer active surface during a processing operation. In one embodiment, the wafer edge ring contains a liquid having a higher refractive index than air while exposing a photoresist on the wafer by immersion lithography. In another embodiment, the wafer edge ring contains a curable liquid material while forming a chip scale package (CSP) sealing layer on the wafer.

Apparatus for spin coating semiconductor substrates

Systems and methods for retrieving residual liquid during immersion lens photolithography are disclosed. A method in accordance with one embodiment includes directing radiation along a radiation path, through a lens and through a liquid volume in contact with the lens, to a microfeature workpiece in contact with the liquid volume. The method can further include, while moving at least one of the microfeature workpiece and the lens relative to the other, recovering liquid from the liquid volume and replenishing liquid in the liquid volume. A spacing between the lens and the microfeature workpiece can be controlled by providing a gas bearing between the lens and the microfeature workpiece. Residual liquid remaining on a surface on the microfeature workpiece can be directed back into the liquid volume, for example, by injecting a gas through at least one injection port that is oriented annularly inwardly toward the liquid volume.

Systems and methods for retrieving residual liquid during immersion lens photolithography

Methods for packaging microfeature devices on and/or in microfeature workpieces at the wafer level and microfeature devices that are formed using such methods are disclosed herein. In one embodiment, a method comprises providing a workpiece including a substrate having a plurality of microelectronic dies on and/or in the substrate. The individual dies include integrated circuitry and pads electrically coupled to the integrated circuitry. The method then includes depositing an underfill layer onto a front side of the substrate. The method also includes selectively forming apertures in the underfill layer to expose the pads at the front side of the substrate. The method further includes depositing a conductive material into the apertures and in electrical contact with the corresponding pads. In one aspect of this embodiment, the underfill layer is a photoimageable material.

Methods for packing microfeature devices and microfeature devices formed by such methods

Method for creating conductive elements for semiconductor device structures using laser ablation processes and methods of fabricating semiconductor device assemblies

Microlenses for directing radiation toward a sensor of an imaging device include a plurality of mutually adhered layers of cured optically transmissive material. Systems include at least one microprocessor and a substrate including an array of microlenses formed thereon in electrical communication with the at least one microprocessor. At least one microlens in the array includes a plurality of mutually adhered layers of cured optically transmissive material.

Growing community of inventors

Boise, ID, United States of America

Peter A Benson