Advanced Micro Devices Corporation

Other

Pervaiz Sultan

Steven C Avanzino

Robin W Cheung

Darrell M Erb

Rich K Klein

A method of forming low dielectric insulation between those pairs of conductive lines, of a level of interconnection for integrated circuits, having a gap of about 0.5 microns or less by depositing a nonconformal source with a poor step function for the insulating material, such as silane (SiH.sub.4) as the silicon (Si) source for silicon dioxide (SiO.sub.2), so as to create, in the gap, a large void whose dielectric constant is slightly greater than 1. After the formation of the void in the 0.5 microns or less gaps, the deposited nonconformal material is etched either simultaneously or sequentially along with deposition to fill the remaining gaps with void free insulation. The surface of the deposited insulating material is planarized at the desired thickness. Alternatively, a thin conformal insulating layer is first deposited as a liner on the conductive lines. The resulting structure of the interconnection level comprises a layer of insulation between and on the conductive lines with the dielectric constant of the insulation between the pairs of conductive lines with gap of 0.5 or less being, in combination with the void, at least about 3 or lower, and all of the remaining gaps are filled with void free insulating material with a dielectric constant of greater than about 3.5.

Bias plasma deposition for selective low dielectric insulation

An improved interconnect space filling process which provides voidless space filling for aspect ratio .ltoreq.1.88 by adding one step to the prior art process to change the aspect ratio of the space to be within specification aspect ratios for the older process. The added step is to apply a highly viscous single spin of SOG after applying a thin CVD PETEOS layer overtop the metallization.

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Pervaiz Sultan