International Business Machines Corporation

Peruvemba S Balasubramanian

Nathan J Lee

Scott Douglas Lekuch

Stephen B Greenspan

Richard F Sapper

Samuel A Lucente

Robert P Latham

Edwin C Grazier

John David Henke

Claude R Bertin

Krishnamurthi Venkataraman

Martin J Myers

Biphase or FM encoding is combined with Flash modulation in infrared (IR) communication. By shrinking the coded pulse width in the modulation process, power dissipation is effectively reduced to the point where FM encoding can be advantageously adapted to IR communication in a synchronous communication system. Noise filtering is also described.

IR FM modem with flash modulation

A modulation scheme and system, compatible with both the asynchronous IRDA mode and the synchronous mode of IR communication, involves Non-Return-to-Zero-Inverted (NRZI) and Flash pulse encoding in conjunction with zero-bit stuffing. A digital data stream has a zero-bit inserted therein, before NRZI format encoding, whenever five consecutive one's are detected in the stream to enable the controller to distinguish the data from flags, which are exempt from the zero-bit insertion, and to provide enough transitions in the data so that the demodulator's digital phase lock loop can stay locked independent of the data contents. A Flash pulse (of from 3/16 to 8/16 of bit cell width, depending on the data rate) is generated whenever a transition is detected in the NRZI formatted data. The result, in keeping with IRDA modulation, is that a Flash pulse is generated whenever a zero occurs in the data stream. On the demodulation side, whenever a Flash pulse is received, the level of the receive line is toggled resulting in an output in NRZI format. Using this modulation scheme with a serial controller which supports NRZI and bit-stuffing, a system may be constructed that uses the controller's phase lock loop to send and receive data synchronously.

Flash NRZI infrared modem

A pen-based computer including a housing and a flat display integral therewith. The flat display can display an image corresponding to text, data and graphic information in several orientations. A plurality of switches enables the user to select an orientation for the image relative to the orientation of the flat display. In one embodiment the switches are mercury switches positioned to automatically align the orientation of the image relative to motion of the flat panel display relative to the force of gravity. An optional additional switch resets the orientation of the image to a predetermined orientation or prevents the reorientation of the image responsive to the mercury switches.

Rotatable pen-based computer with automatically reorienting display

A directed infrared (IR) communication controller which supports interoperability among protocols and which can communicate at baud rates of up to 2.34 Mbps while supporting the IRDA standard as well as Sharp's 500 KHz ASK, NRZI, and Biphase modulated IR systems. A method for automatically determining which type of infrared signal is being received is also described.

Multiprotocol directed infrared communication controller

Amplitude Shift Keying (ASK) modulation system and method with an ASK demodulator that is implemented with an analog-emulating digital bandpass filter. The bandpass filter also generates a carrier detect signal when it detects a carrier frequency that passes the filter pass band.

ASK demodulator implemented with digital bandpass filter

A pen-based computer includes a housing and a flat panel display integral therewith. The computer housing has a slanted parallelpiped configuration with polyhedron-shaped top and bottom surfaces and parallelogram-shaped side and end surfaces interconnecting the top and bottom surfaces. The side and end surfaces of the housing include one adjacent side and end surface having an upward exposure, and another adjacent side and end surface having a downward exposure, with each of the side and end surfaces extending at an angle of between about 10 and 45 degrees from the top surface to the bottom surface. The flat panel display for the computer is mounted proximate to the top surface of the housing proximate one corner, and the bottom surface of the housing is designed to be supported on a horizontal support surface. The computer housing has a configuration which enables a right-handed user to orient the housing in at least one orientation such that the upwardly facing side and end surfaces are located along the right side and upper or lower ends of the housing to enable the right-handed user to comfortably use the computer, and to enable a left-handed user to orient the housing in at least one other orientation such that the upwardly facing side and end surfaces are located along the left side and upper or lower ends of the housing to enable a left-handed user to easily grasp and utilize the computer. A switch enables the user to correctly align text, data and graphic information on the flat panel display with the particular orientation of the computer.

Rotatable pen-based computer

A write once, read only electrically programmable storage circuit is disclosed, which employs a flip-flop circuit to store the programmed conductive state of the array device, by means of a blocking transistor connected between the array device and one node of the flip-flop, the control electrode of the blocking transistor being connected to the other node of the flip-flop. With the flip-flop having an initial first state so that the blocking device is conductive, a precharged signal may be conducted through the array device to ground indicating a first stored information state. By driving a write signal through the array device and the blocking device, of sufficient magnitude to set the flip-flop in its opposite state, the blocking device is then made nonconductive and subsequent attempts to transmit a precharge signal through the array device to ground, will not be possible, indicating a second stored information state. This basic storage circuit is inclined as the array cell in a programmable PLA chip architecture which requires only four additional pins beyond the mask programmable version. This is accomplished by the dual use of the output latches of the OR array for both reading out the array and for programming the array by a scan-in technique. Cells in the AND array are programmed by a product term programmer register which allows product terms to be programmed by input partitioning circuits.

Electrically programmable logic array

An array of parallel FET load circuits on an IC (integrated circuit) chip can have their respective signal delays equalized where their nodal capacitances are different or alternately can have their signal delays set for different durations to meet the needs of a subsequent circuit, by adjusting the current driving capacity of a driver driving each circuit to meet the desired delay requirements thereof.

Generalized performance power optimized PLA circuits

A merged AND/OR array PLA is disclosed wherein the merger is accomplished by forming the gates of the FET devices in the AND array by means of an upper conductor layer and the gates of the FET devices in the OR array, which are connected to the drain of the devices in the AND array, by means of lower level conductor layer, so that the devices are contiguous. The PLA structure uses a polysilicon layer for interconnection between AND array FET drains and OR array FET gates, with the AND array FETs or OR array FETs being intermixed in a single array. The OR array outputs are oriented vertically, alternating between the AND product terms and ground diffusions. All PLA outputs are oriented vertically within the same array. A testing technique and special testing circuitry is disclosed which makes use of the existing bit partitioning input buffer as the source of test patterns and the existing output latches as the storage for the test response bits for individually testing both the AND components and the OR components in the merged array PLA.

Growing community of inventors

Chappaqua, NY, United States of America

Peruvemba S Balasubramanian