Texas Instruments Corporation

Brooktree Corporation

Silanna Semiconductor U.s.a., Inc.

Qualcomm Incorporated

Semtech Corporation

Io Semiconductor, Inc.

Qualcomm Switch Corp.

Idesco Oy

Perry Wyan Lou

Stuart B Molin

Clint L Kemerling

Graham S Tubbs

James E Ponder

Sinan Goktepeli

Lanny L Lewyn

George L Brantingham

Clint Kemerling

Ki S Chang

Charles P Grant, Jr, Deceased

Jeffrey R Teza

Stephen A Farnow

Lawrence J Housey, Jr

Aman Khosrovi

An integrated circuit device may include a front-side contact coupled to a front-side metallization. The integrated circuit device may further include a backside contact coupled to a backside metallization. The front-side contact may be directly coupled to the backside contact.

Substrate contact using dual sided silicidation

Various methods and devices that involve power-on-reset (POR) circuits are disclosed herein. An exemplary POR circuit for generating a POR signal upon detecting that a supply voltage has reached a desired level comprises a sense circuit and a delayed buffer. The sense circuit comprises: (i) an inverter powered by a known bias voltage; (ii) a feedback circuit powered by the supply voltage; and (iii) an output node of the sense circuit that experiences a voltage transition when the supply voltage has reached the desired level. The delayed buffer is coupled to the output node of the sense circuit that generates the POR signal in response to the voltage transition. The feedback circuit shuts off the sense circuit in response to the voltage transition. The POR circuit generates the POR signal for a local system. The known bias voltage is provided by an external system.

Low power externally biased power-on-reset circuit

A charge pump regulator circuit includes an oscillator and one or more charge pumps. One or more oscillating signals are generated by the oscillator. Each oscillating signal has a peak-to-peak amplitude that is variable dependent on a variable drive signal. For some embodiments having multiple oscillating signals, each oscillating signal is phase shifted from a preceding oscillating signal. For some embodiments having multiple charge pumps, each charge pump is connected to receive a corresponding one of the oscillating signals. Each charge pump outputs a voltage and current. For some embodiments having multiple charge pumps, the output of each charge pump is phase shifted from the outputs of other charge pumps. A combination of the currents thus produced is provided at about a voltage level to a load.

Charge pump regulator circuit

A charge pump regulator circuit includes an oscillator and one or more charge pumps. One or more oscillating signals are generated by the oscillator. Each oscillating signal has a frequency or amplitude or both that are variable dependent on a variable drive signal. For some embodiments having multiple oscillating signals, each oscillating signal is phase shifted from a preceding oscillating signal. For some embodiments having multiple charge pumps, each charge pump is connected to receive a corresponding one of the oscillating signals. Each charge pump outputs a voltage and current. For some embodiments having multiple charge pumps, the output of each charge pump is phase shifted from the outputs of other charge pumps. A combination of the currents thus produced is provided at about a voltage level to a load.

Charge pump regulator circuit with variable amplitude control

A charge pump regulator circuit includes a voltage controlled oscillator and a plurality of charge pumps. The voltage controlled oscillator has a plurality of inverter stages connected in series in a ring. A plurality of oscillating signals is generated from outputs of the inverter stages. Each oscillating signal has a frequency or amplitude or both that are variable dependent on a variable drive voltage. Each oscillating signal is phase shifted from a preceding oscillating signal. Each charge pump is connected to a corresponding one of the inverter stages to receive the oscillating signal produced by that inverter stage. Each charge pump outputs a voltage and current. The output of each charge pump is phase shifted from the outputs of other charge pumps. A combination of the currents thus produced is provided at about a voltage level to the load.

Charge pump regulator circuit with a variable drive voltage ring oscillator

Embodiments of the present invention provide a device for level shifting an input signal. The device includes an output buffer that has: an output node, a p-FET coupled to a high reference voltage, and an n-FET coupled to a low reference voltage. The device also includes two latches. The first latch has a first latch output that drives a gate of the p-FET via an inverting circuit element. The second latch has a second latch output that drives a gate of the n-FET via a non-inverting circuit element. The device also includes a reset signal pulse generator that receives the input signal and generates a reset signal pulse in response to a transition in the input signal. Both of the latches are placed in a reset state by the reset signal pulse.

Compact level shifter

Charge pump regulator circuit for powering a variable load

An adaptive output driver circuit utilizes an initial point matched impedance model to match the impedance of an output driver to the transmission line and produce an initial step voltage into the transmission line that is half of the desired final voltage. The driver output impedance is controlled by comparing a model of the actual working output stage to a target resistance given by the user. Control signals used to calibrate the impedance of the model to match the target are also used to adjust the working output buffer, so that when the impedance of the model matches the target, the impedance of the working buffer also matches the target impedance.

Method and system for adaptively controlling output driver impedance

An inverter receives an energizing voltage with a particular magnitude (e.g. 1.5 V) at a first terminal and produces the voltage at a second terminal. The received and produced voltages are differentially introduced to a stage which produces a single-ended bias voltage (e.g. 3 V) related to the second terminal voltage. The bias voltage is servoed to regulate the second terminal voltage (e.g. 1.5 V) and the bias voltage (e.g. 3 V) regardless of energizing voltage variations. In response to the bias voltage and a variable input voltage, a pass transistor in a buffer produces a first control voltage different from the bias voltage by the pass transistor threshold voltage for input voltages greater than the bias voltage less the pass transistor threshold. The first control voltage corresponds to the input voltage for input voltages less than the bias voltage less the pass transistor threshold. The first control voltage is inverted to produce a second control voltage having the first control voltage amplitude for small amplitude values of the first control voltage and having transition times and amplitudes of the first control voltage for large amplitude values of the first control voltage. A circuit differentially responds to the control voltages to produce an output voltage which rises and falls in accordance with the variations in the input voltage. The output voltage is servoed to limit the rises and falls. The output voltage has substantially the same wave shape, and substantially the same delay relative to the input voltage, for rising and falling values.

Regulated reference voltage generator having feedback to provide a

Apparatus for providing an output voltage with substantially identical

An inverter receives an energizing voltage with a particular magnitude (e.g. 1.5 V) at a first terminal and produces the voltage at a second terminal. The received and produced voltages are differentially introduced to a stage which produces a single-ended bias voltage (e.g. 3 V) related to the second terminal voltage. The bias voltage is servoed to regulate the second terminal voltage (e.g. 1.5 V) and the bias voltage (e.g. 3 V) regardless of energizing voltage variations. In response to the bias voltage and a variable input voltage, a pass transistor in a buffer produces a first control voltage different from the bias voltage by the pass transistor threshold voltage for input voltages greater than a value equal to the bias voltage less the pass transistor threshold, and corresponding to the input voltage for input voltages less than the bias voltage less the pass transistor threshold. The first control voltage is inverted to produce a second control voltage having the amplitude of the first control voltage for small amplitude values of the first control voltage, and having transition times and amplitudes of the first control voltage for large amplitude values of the first control voltage. A circuit differentially responds to the control voltage to produce an output voltage which rises and falls in accordance with the variations in the input voltage. The output voltage is servoed to limit the rises and falls.

Input buffer for translating TTL levels to CMOS levels

First and second transistors respectively receive differential input signals each having first and second logic levels and respectively produce resultant currents dependent upon the levels of the input signals. The transistors may be CMOS transistors of the n-type with substantially identical characteristics. The input signals may be introduced to the gates of these transistors and the resultant currents may be produced at the drains of these transistors. Third and fourth transistors may receive the resultant currents. The third and fourth transistors may be CMOS transistors of the n-type with substantially identical characteristics. The resultant voltage at the first transistor may be introduced in a modified form to the third and fourth transistors to regulate the resultant voltage introduced to the third transistor and to expedite the response of the fourth transistor. The modification may be an inversion of the resultant voltage at the first transistor, the inversion being produced by an amplifier-inverter in a servo loop with the third transistor. The currents on the drains of the first and second transistors may be respectively introduced to the sources of the third and fourth transistors. The modified (or inverted) voltage from the drain of the first transistor may be introduced to the gates of the third and fourth transistors. An output voltage may be provided at the source of the fourth transistor. The output voltage may be inverted as by an amplifier-inverter having characteristics substantially identical to those of the amplifier-inverter in the servo loop.

Differential-to-single-ended converter

Three delay lines may have common characteristics. The first delay line delays the rising edge of an input signal and a first inverter inverts this signal to provide a falling edge. A second inverter inverts the rising edge of the input signal to produce a falling edge which is introduced to the second delay line in a second path with the second inverter. The signals from the two paths may be introduced to a comparator which produces a control signal having logic levels dependent upon the relative times that the falling edges occur for the signals in the two paths. For example, the control signal may have the first logic level when the falling edge occurs first in the first path and the control signal may have the second logic level when the falling edge occurs first in the second path. The voltage from a charge pump is adjusted in accordance with the logic level of the control signal. This voltage is introduced to the first and second delay lines to adjust their delay to minimize the time difference in the falling edges of the signals from these lines. This voltage is also introduced to the third delay line to adjust its delay in accordance with the adjustments in the delays in the first and second lines. In this way, the third delay line provides the same time for rising edges and falling edges in data signals introduced to the line.

Regulated delay line

A system for regulating an output voltage to a particular value includes a control transistor which produces an output voltage when energized by an energizing voltage. A voltage divider formed as by a pair of transistors with a particular ratio of transconductances divides the magnitude of this output voltage by a ratio related to the ratio of the transconductances. The transistors in the voltage divider may be respectively CMOS n- and p- transistors. The divided output voltage is introduced to a comparator (formed as from a pair of transistors) for comparison with a fixed reference voltage obtained as from a resistance ladder energized by the energizing voltage. The comparator introduces voltages to a comparator amplifier in accordance with such comparison. The comparator amplifier may include a transistor which produces changes in a current related to changes in the divided output voltage. The comparator amplifier may further include a current mirror which provides changes in a current related to changes in the current through the amplifier transistor. The current changes in the current mirror cause changes to be produced in a voltage (e.g. error voltage) from the current mirror. These error voltage changes are introduced to the control transistor to regulate the output voltage to the particular value.

Voltage regulator

An enhancement mode field effect transistor and a depletion mode field effect transistor are connected in a circuit to provide for a conductivity of the transistors during a first polarity in an alternating voltage and to provide for a non-conductivity of the transistors during a second polarity in the alternating voltage. The circuit also provides for the continued and proper operation of the circuit even when voltages having a magnitude greater than the breakdown voltage of the enhancement mode field effect transistor are applied to the circuit. Each of the transistors may have a source, a gate and a drain. The gates of the transistors receive an alternating voltage of one polarity at the same time that the drain of the depletion mode field effect transistor receives a voltage of the opposite polarity. The source of the depletion mode field effect transistor and the drain of the enhancement mode field effect transistor are common. The source of the enhancement mode field effect transistor may receive a reference potential such as ground. The transistors are conductive during the application of a positive voltage to their gates and are non-conductive during the application of a negative voltage to their gates. When the transistors are non-conductive, the depletion mode transistor prevents the voltage on the drain of the enhancement mode field effect transistor from exceeding the breakdown value.

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Carlsbad, CA, United States of America

Perry Wyan Lou