Qualcomm Incorporated

Microsoft Technology Licensing, LLC

International Business Machines Corporation

Perry Willmann Remaklus, Jr

Robert Michael Walker

Richard Gerard Hofmann

Jaya Prakash Subramaniam Ganasan

J Prakash Subramaniam Ganasan

Thomas Philip Speier

Eric Francis Robinson

Garrett M Drapala

Joseph Gerald McDonald

Mark Michael Schaffer

Majid Anaraki Nemati

Prudhvi Nadh Nooney

Srikanth Dakshinamoorthy

Ravinder Kumar

Nikhil Narendradev Sharma

Mattheus Cornelius Antonius Adrianus Heddes

Adger Erik Harvin, Iii

Providing media power telemetry for virtual machines (VMs) in processor-based devices is disclosed herein. In one exemplary embodiment, a processor-based device provides a controller circuit comprising a power telemetry circuit, and a power management processor. The power telemetry circuit is configured to determine whether a media access request corresponding to a power telemetry event and directed to a media device is detected, and determine whether the media access request matches an event selection filter specified by an event selection control and status register (CSR) corresponding to the power telemetry event. If so, the power telemetry circuit increments a power telemetry counter corresponding to the power telemetry event by a relative power value associated with a media access request type of the media access request. The power management processor determines a power management operation based on the power telemetry counter corresponding to the power telemetry event, and applies the power management operation.

Providing media power telemetry for virtual machines (VMs) in processor-based devices

Embodiments of the present disclosure include techniques for encoding and decoding metadata in error correction codes. During read operation, a decoder generates a first output corresponding to the at least one metadata bit having a first state and a second output corresponding to the at least one metadata bit having a second state. When one of the first and second outputs have a zero value, the decoder sets a value of the at least one metadata bit to the first state or the second state corresponding to the first output or the second output having the zero value. When both the first and second outputs are non-zero, the decoder decodes the codeword with the assumption of both the metadata bit having the first state and the second state to determine if the codeword is correctable with the at least one metadata bit.

Decoding metadata encoded in error correction codes

Selective honoring of speculative memory-prefetch requests based on bandwidth constraint of a memory access path component(s) in a processor-based system. To reduce memory access latency, a CPU includes a request size in a memory read request of requested data to be read from memory and a request mode of the requested data as required or preferred. A memory access path component includes a memory read honor circuit configured to receive the memory read request and consult the request size and request mode of requested data in the memory read request. If the selective prefetch data honor circuit determines that bandwidth of the memory system is less than a defined bandwidth constraint threshold, then the memory read request is forwarded to be fulfilled, otherwise, the memory read request is downgraded to only include any requested required data.

Selectively honoring speculative memory prefetch requests based on bandwidth state of a memory access path component(s) in a processor-based system

Providing efficient lossless compression for small data blocks in processor-based systems is provided. In one aspect, a method comprises receiving a plurality of input words. Each mask of a plurality of masks is applied to each unassigned input word to generate a corresponding plurality of patterns. For each mask, if a most frequently occurring pattern exists among the plurality of patterns, the most frequently occurring pattern and an uncompressed data portion of each unassigned input word are stored in association with a prefix associated with the mask. The prefix is also assigned to each unassigned input word corresponding to the most frequently occurring pattern. A compressed output block is generated, comprising prefixes assigned to the plurality of input words, the most frequently occurring patterns associated with the assigned prefixes, and uncompressed data portions corresponding to one or more input words of the plurality of input words.

Providing efficient lossless compression for small data blocks in processor-based systems

Processor-based system hybrid ring bus interconnects, and related devices, systems, and methods are disclosed. In one embodiment, a processor-based system hybrid ring bus interconnect is provided. The processor-based system hybrid ring bus interconnect includes multiple ring buses, each having a bus width and configured to receive bus transaction messages from a requester device(s). The processor-based system hybrid ring bus interconnect also includes an inter-ring router(s) coupled to the ring buses. The inter-ring router(s) is configured to dynamically direct bus transaction messages among the ring buses based on bandwidth requirements of the requester device(s). Thus, less power is consumed than by a crossbar interconnect due to simpler switching configurations. Further, the inter-ring router(s) allows for provision of multiple ring buses that can be dynamically activated and deactivated based on bandwidth requirements. This provides conservation of power when full bandwidth requirements on the processor-based system hybrid ring bus interconnect are not required.

Processor-based system hybrid ring bus interconnects, and related devices, processor-based systems, and methods

A memory system, and process for refreshing the memory, is disclosed. The memory system includes memory, a temperature sensor configured to measure the temperature of the memory, and a memory controller configured to refresh the memory at a refresh rate, the refresh rate being controlled as a function of the temperature measured by the temperature sensor.

Refreshing dynamic volatile memory

In a directed auto-refresh (DARF) mode, refresh commands are issued by a controller, and refresh row and bank addresses are maintained internally to a memory module. A bank address counter internal to the memory is initialized to a first predetermined value upon entering DARF mode. The memory refreshes the currently addressed bank in response to a DARF command, and increments the bank address counter in a predetermined sequence. The controller tracks the bank address, and may issue one or more memory access commands while a DARF operation is being performed, if the memory access and the refresh are directed to different banks. Upon exiting a self-refresh mode, the bank address counter assumes a second predetermined value. The second predetermined value may be fixed, or may be n+1, where n is the value of the bank address counter when self-refresh mode is initiated.

Directed auto-refresh synchronization

A memory system is provided. The memory system includes a volatile memory having a number of banks and a memory controller configured to control the volatile memory to engage in an auto-refresh mode or a self-refresh mode. The memory controller is further configured to direct the volatile memory to perform an auto-refresh operation on a target bank. The remaining banks are available for access while the auto-refresh operation is being performed on the target bank.

Method and system for providing directed bank refresh for volatile memories

A memory system is provided. The memory system includes a volatile memory having a number of banks, each bank having a number of rows, and a memory controller configured to direct the volatile memory to engage in an auto-refresh mode, the memory controller further configured to provide a target bank address to the volatile memory. The volatile memory is configured to perform an auto-refresh operation in the auto-refresh mode, the auto-refresh operation being performed on a target bank identified by the target bank address. Remaining banks in the plurality of banks other than the target bank are available for memory access while the auto-refresh operation is being performed on the target bank.

Method and system for providing independent bank refresh for volatile memories

Embodiments of the invention are directed to a method and apparatus for reducing transfer latency in a system on a chip, the system on a chip comprising a bus master, a bus slave and an arbiter, wherein the bus master, bus slave and arbiter are in electronic communication therebetween. A request is transmitted from the bus master to the arbiter, wherein a priority signal is associated with a latency requirement. The arbiter reviews the latency requirement prior to transmitting the request to the bus slave and determines whether to elevate the priority signal. The request signal is then transmitted from the arbiter to the bus slave. The bus slave fulfills the request and transmits a response to the request, wherein the transmission includes the priority signal.

Method and apparatus of reducing transfer latency in an SOC interconnect

A system-on-chip (SoC) integrated circuit (IC) has reduced bus contention and improved bus utilization. The SoC IC includes a bus controller. Masters interconnected with the bus controller issue requests for data and receive requested data in response to the requests. Slaves interconnected with the bus controller receive the requests for data and provide the requested data to the requesting masters. Control signals issued by the bus controller indicate to each slave which masters are not ready to receive the data it requested from that slave. The slaves delay transferring data to any masters that are not ready for the requested data, and provide data to different masters that are ready to receive the data they requested from the slaves.

Flow control method to improve bus utilization in a system-on-a-chip integrated circuit

A memory system is provided. The system includes a volatile memory having a number of banks and configured to engage in one of a number of operating modes including an auto-refresh mode and a self-refresh mode, and a memory controller configured to direct the volatile memory to engage in one of the operating modes. Upon the memory controller directing the volatile memory to engage in the self-refresh mode, the memory controller is further configured to provide an entry bank address to the volatile memory, the entry bank address corresponding to the first bank that is to be refreshed during the self-refresh mode. Upon the volatile memory exiting the self-refresh mode, the volatile memory is further configured to make an exit bank address available to the memory controller, the exit bank address corresponding to the last bank that was refreshed prior to the volatile memory exiting the self-refresh mode.

Method and system for providing seamless self-refresh for directed bank refresh in volatile memories

A bus performance monitoring mechanism for systems on a chip (SOC) is disclosed. The system comprises a muxing logic adapted to be coupled to a plurality of master devices, a plurality of slave devices, a plurality of generic signals and a plurality of control signals. The monitoring mechanism includes a plurality of control registers coupled to the muxing logic to allow for the selection of master, slave, generic and pipeline stage events to be counted. Finally, the monitoring mechanism includes synchronizing logic coupled to the plurality of registers for providing and receiving synchronizing signals to and from the monitors coupled thereto to allow for scalability. The scalable on-chip bus performance monitoring system in accordance with the present invention performs on-chip bus monitoring within a SOC implementation, while eliminating the pitfalls as described above. Through a minimalistic design approach, scalability is easily accomplished through the concept of using multiple monitor instances of these monitoring mechanisms within an SOC design while maintaining synchronization among them. Should an SOC design increase in size, scalability is achieved by simply adding additional monitor instance(s). The multiple monitor instances could then be connected in a 'lego-like' fashion, allowing each to operate independently, or concurrently with one another via a scalable synchronization technique. For these designs where multiple monitor instances may be required, this enhances wireability by allowing the SOC designer to scatter the monitor instance locations virtually anywhere within the smaller areas of unused chip space, and simply wire the synchronization signals among the monitor instances to allow for synchronous operation.

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Raleigh, NC, United States of America

Perry Willmann Remaklus, Jr