Hewlett-Packard Development Company, L.p.

Perry M Wyatt

Daniel Alan Berkram

David Thomas Newsome

Multiphase clock generating apparatus includes a multiplexer selecting one of a generated clock and a gated generated clock as an M-clock in accordance with a halt multiplexer control. Divider circuitry provides an alignment signal corresponding to an inverted M-clock divided by M. A recovery circuit recovers up to M distinct clocks from the M-clock in accordance with the alignment signal. The recovered clocks have a 180&#xb0;/M relative phase difference. A halt circuit controls the halt multiplexer control to select the gated generated clock when a selected recovered clock matches a pre-determined clock level. The halt multiplexer control is clocked by the generated clock.

Method and apparatus for generating and controlling a multiphase clock

A multiphase clock generating apparatus includes a clock generator providing an M-clock having a frequency M times that of a received reference clock. Divider circuitry is coupled to provide an alignment signal having 1/M the frequency of the M-clock. A recovery circuit recovers up to M distinct clocks from the M-clock in accordance with the alignment signal. The recovered clocks have substantially an N&#x2022;&#xb0;/M phase difference from each other, wherein N&#x2267;

Method and apparatus for generating a multiphase clock

A method of measuring jitter includes generating a jitter pulse having a width corresponding to an amount of jitter. The jitter pulse is provided to a plurality (M) of latches serially coupled to successively trim the pulse as it propagates through the serially coupled latches. Each latch, l, provides an output bindicative of receipt of an edge of the jitter pulse.

Method and apparatus for measuring jitter

Quadrature clock generating apparatus includes a multiplexer selecting one of a generated clock and a gated generated clock as a double clock in accordance with a halt multiplexer control. Divider circuitry provides an alignment signal corresponding to an inverted double clock divided by two. A recovery circuit recovers first and second clocks having a 90&#xb0; phase difference from the double clock in accordance with the alignment signal. A halt circuit controls the halt multiplexer control to select the gated generated clock when the alignment signal matches a pre-determined clock level. The halt multiplexer control is clocked by the generated clock.

Method and apparatus for generating and controlling a quadrature clock

A quadrature dock generating apparatus includes a clock generator providing a double clock having a frequency that is twice that of a received reference clock. Divider circuitry is coupled to provide an alignment signal having half the frequency of the double clock. A recovery circuit recovers a first clock and a second clock from the double clock in accordance with the alignment signal. The first and second clocks have substantially a 90&#xb0; phase difference.

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Fort Collins, CO, United States of America

Perry M Wyatt