Intel Corporation

Cirrus Logic Inc.

Vintomie Networks B.v., LLC

Perry Leigh Heedley

Kenneth Colin Dyer

Baker P Scott

Eric Kimball

Eric B Smith

Stephen Timothy Hodapp

James Little

Sumant Ranganathan

Mohammad Navabi

David Vieira

Maoyou Sun

A low spur phase-locked loop (PLL) architecture is provided. A frequency-synthesizing PLL that includes a differential Kvco gain linearization circuit with adjustable DC offset is used to reduce clock jitter. The free-running oscillation frequency of the VCO of the PLL is centered near the desired frequency using programmable loads to minimize the required control voltage range. The PLL uses a differential architecture that includes a charge pump that compensates for variations in Kvco and a LC tank oscillator with differential controlled varactor. The differential PLL architecture demonstrates that the reference spur can be well controlled to below &#x2212;80 dBc.

Low spur phase-locked loop architecture

An operational amplifier circuit that provides negative feedback and high gain is described. Specifically, the circuit comprises a first gain stage, a second gain stage, a feedback circuit, and a biasing circuit.

Common mode feedback circuit for fully differential two-stage operational amplifiers

A biasing technique between a first circuit stage and a second circuit stage is described. Specifically, the technique comprises using a combination of thin and thick oxide transistors.

Biasing technique using thin and thick oxide transistors

A multi-path unity gain buffer circuit and method are implemented in a slew amplifier. The multi-path unity buffer has a high frequency signal path and a low frequency signal path. The high frequency signal path has a differential amplifier powered for providing a high frequency, low accuracy buffering operation. The low frequency signal path is coupled to the high frequency signal path. The low frequency signal path has an operational amplifier powered to provide a low frequency, high bandwidth buffering operation. An output of the operational amplifier is fed back to an input of the operational amplifier through a current varying element that varies current levels of the input of the operational amplifier to remove a level shift of an output signal of the differential amplifier.

Output driver for a 10baset/100basetx ethernet physical layer line interface

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Folsom, CA, United States of America

Perry Leigh Heedley