Intel Corporation

Other

Perry H Wang

Hong Wang

John P Shen

Per H Hammarlund

Jamison D Collins

Xinmin Tian

Milind Baburao Girkar

John Thomas Shen

Steve Shih-wei Liao

Gerolf F Hoflehner

Edward Thomas Grochowski

Gautham N Chinya

Xiang Chris Zou

James Paul Held

Partha Kundu

Tin-Fook Ngai

Raya Leviathan

Daniel M Lavery

Piyush N Desai

Wei Ey Li

Tor M Aamodt

Shih-wei Liao

Dongkeun Kim

Richard A Hankins

Ralph Michael Kling

George Zacharias Chrysos

Doron Orenstein

Jared Warner Stark, Iv

Pedro Marcuello

Deepak A Mathaikutty

Ed Grochowski

Marsha Eng

Jeffery A Brown

Hong Jiang

Guei-Yuan Lueh

Gad Shlomo Sheaffer

Koichi Yamada

Tsung-Han Lin

David Sehr

Asit K Mallick

Antonio Gonzalez

Chris J Newburn

Jeffrey D Chamberlain

Bryan P Black

Antonio González

Stephen J Robinson

Sanjiv M Shah

Debabrata Mohapatra

Roni Rosner

Gokce Keskin

Bernard Lint

Satish Narayanasamy

Thiam Wah Loh

Eckhard Delfs

Sang Kyun Kim

Stephen J Tarsa

Andreas Wasserbauer

William R Greene

Yoav Almog

Grant E Haab

Alejandro Ramirez

Reza Fortas

Hideki Saito

Dan Lavery

Neil A Chazin

Ralph M King

Swee Chong Peter Kuan

Chee Weng Tan

Jamison D Colins

Daniel LaVery

Geolf F Hoflehner

Michael D Linderman

Richard Grove

Tor Aamodt

Ashok N Seshadri

Anthony N Mah

Ravi K Chandran

Naftali Schwartz

Natalie D Enright

Xinmin Tran

Gerolf Hoflehner

A processor includes a front end including circuitry to decode a first instruction to set a performance register for an execution unit and a second instruction, and an allocator including circuitry to assign the second instruction to the execution unit to execute the second instruction. The execution unit includes circuitry to select between a normal computation and an accelerated computation based on a mode field of the performance register, perform the selected computation, and select between a normal result associated with the normal computation and an accelerated result associated with the accelerated computation based on the mode field.

Arithmetic logic unit with normal and accelerated performance modes using differing numbers of computational circuits

Method, apparatus, and program means for a programmable event driven yield mechanism that may activate other threads. In one embodiment, an apparatus includes execution resources to execute a plurality of instructions and a monitor to detect a condition indicating a low level of progress. The monitor can disrupt processing of a program by transferring to a handler in response to detecting the condition indicating a low level of progress. In another embodiment, thread switch logic may be coupled to a plurality of event monitors which monitor events within the multithreading execution logic. The thread switch logic switches threads based at least partially on a programmable condition of one or more of the performance monitors.

Programmable event driven yield mechanism which may activate other threads

A method and system to provide user-level multithreading are disclosed. The method according to the present techniques comprises receiving programming instructions to execute one or more shared resource threads (shreds) via an instruction set architecture (ISA). One or more instruction pointers are configured via the ISA; and the one or more shreds are executed simultaneously with a microprocessor, wherein the microprocessor includes multiple instruction sequencers.

Method and system to provide user-level multithreading

Implementations of the disclosure provide a processing device comprising a branch predictor circuit to obtain a branch history for an application. The branch history comprising references to branching instructions associated with the application and an outcome of executing each branch. Using the branch history, a neutral network is trained to produce a weighted value for each branch of the branching instructions. Features of the branching instructions are identified based on the weighted values. Each feature identifying predictive information regarding the outcome of at least one branch of correlated branches having corresponding outcomes. A feature vector is determined based on the features. The feature vector comprises a plurality of data fields that identify an occurrence of a corresponding feature of the correlated branches with respect to the branch history. Using the feature vector, a data model is produced to determine a predicted outcome associated with the correlated branches.

Supporting learned branch predictors

Systems, Methods and apparatuses relating to processor cores that respond to interrupts are disclosed. In one embodiment, an apparatus includes an interrupt interface, a memory interface; and a processor core to generate an interrupt acknowledge signal in response to a received interrupt; receive data in return; determine whether the received data is an interrupt service routine address, the interrupt service routine address being stored in an interrupt vector translation lookaside buffer; and, if not, use the received data to calculate the interrupt service routine address; wherein the processor core is further to use the interrupt service routine address to issue a request on the memory interface to fetch the interrupt service routine, and to execute the interrupt service routine.

Interrupt-vector translation lookaside buffer

Systems and methods for employing hardware-assisted virtualization for implementing a secure video output path. An example processing system comprises: a memory; a shared interconnect; and a processing core communicatively coupled to the memory via the shared interconnect, the processing core to: initialize a first virtual machine and a second virtual machine; responsive to receiving a memory access transaction initiated by the first virtual machine to access a memory buffer, tag the memory access transaction with an identifier of the first virtual machine; and responsive to receiving a digital content decoder access transaction initiated by the second virtual machine, tag the digital decoder access transaction with an identifier of the second virtual machine.

Hardware-assisted virtualization for implementing secure video output path

Method and system to provide concurrent user-level, non-privileged shared resource thread creation and execution

Growing community of inventors

San Jose, CA, United States of America

Perry H Wang