Freescale Semiconductor,inc.

Perry H Pelly

Carlos A Greaves

A memory () has a plurality of memory cells, a serial address port () for receiving a low voltage high frequency differential address signal, and a serial input/output data port () for receiving a high frequency low voltage differential data signal. The memory () can operate in one of two different modes, a normal mode and a cache line mode. In cache line mode, the memory can access an entire cache line from a single address. A fully hidden refresh mode allows for timely refresh operations while operating in cache line mode. Data is stored in the memory array () by interleaving in multiple sub-arrays (). During a hidden refresh mode of operation, one sub-array () is accessed while another sub-array () is refreshed. Two or more of the memories () may be chained together to provide a high speed low power memory system.

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Austin, TX, United States of America

Perry H Pelly