Freescale Semiconductor,inc.

Motorola Corporation

Nxp Usa, Inc.

Molorola, Inc.

Perry H Pelley

Michael B McShane

Tab Allen Stephens

Ravindraraj Ramaraju

George P Hoekstra

Anirban Roy

Kevin John Hess

James David Burnett

Frank Kelsey Baker, Jr

Tim V Pham

Hamed Ghassemi

Scott G Nogle

Lucio F C Pessoa

Andrew Christopher Russell

William C Moyer

Prashant U Kenkare

Bruce L Morton

John M Burgan

Peter Jeremy Wilson

Troy L Cooper

Ruey J Yu

Thomas W Liston

Michael A Mendicino

Robert C Taft

Michael Garrett Neaves

Alan J Lewandowski

Sam Dehganpour

Shahnaz P Chowdhury-Nagle

Stephen T Flannagan

Paul Grudowski

John D Coddington

Peter R Harper

Tu-Anh N Tran

Bradley J Garni

Sheila F Chopin

Carlos A Greaves

Gayathri Bhagavatheeswaran

Yaping Zhou

Susan H Downey

Bruce E Engles

Alan H Woosley

Steven C Sullivan

Dennis C Hartman

James R Guajardo

Jeremiah T C Palmer

Tim P Egging

Kevin Tran

Lucio F Pessoa

A memory circuit includes a plurality of memory tiles. Each memory tile in the plurality of memory tiles includes a plurality of bit cells and a control circuit coupled to the plurality of bit cells. The control circuit is configured to provide latched data to the plurality of bit cells during write operations. A first write control line is coupled to the control circuit in a first memory tile, and the first write control line is configured to initiate a first write operation in the first memory tile. And a second write control line is coupled to the control circuit in a second memory tile, and the second write control line configured to initiate a second write operation in the second memory tile. The second write operation may be initiated before the first write operation is completed.

Memory circuit having concurrent writes and method therefor

An integrated circuit includes an array of resistive non-volatile memory cells having a plurality of word lines, a plurality of bit lines, and a plurality of source lines. The integrated circuit includes a sense amplifier coupled to a first bit line of the plurality of bit lines and a corresponding first source line of the plurality of source lines. When a memory cell coupled to the first bit line is selected for a read operation, the sense amplifier is configured to, during a calibration phase of the read operation, store a first voltage representative of a leakage current on the first source line. The sense amplifier is also configured to, during a sense phase of the read operation, apply the stored first voltage to the first bit line and provide a first sense amplifier output indicative of a logic state of the selected memory cell.

Resistive non-volatile memory and a method for sensing a memory cell in a resistive non-volatile memory

An integrated circuit optical die test interface and associated testing method are described for using scribe area optical mirror structures () to perform wafer die tests on MEMS optical beam waveguide () and optical circuit elements () by perpendicularly deflecting optical test signals () from the scribe area optical mirror structures () into and out of the plane of the integrated circuit die under test () and/or production test die ().

Optical die test interface with separate voltages for adjacent electrodes

A semiconductor device includes an array of memory cells, and a reference voltage generation circuit including a first set of reference memory cells coupled to a first bit line, a second set of reference memory cells coupled to a second bit line, a first capacitor having a first terminal coupled to the first bit line, and a second terminal, a second capacitor having a first terminal coupled to the second terminal of the first capacitor at a first node and a second terminal coupled to the second bit line, an amplifier including a first input selectively coupled to the first node and a second input coupled to an output of the amplifier that provides reference voltage used by sense amplifiers, and a third capacitor including a first terminal coupled to the output of the amplifier and a second terminal coupled to a first supply voltage.

The dies of a stacked die IC are tested and, in response to detection of a defect at one of the dies, the type of defect is identified. If the defect is identified as a defective module repairable at the die itself, a redundant module of the die is used to replace the functionality of the defective module. If the defect is identified as one that is not repairable, a replacement die in the die stack is used to replace the functionality of the defective die.

Defective die replacement in a die stack

A memory system includes a main memory array, a redundant memory array, and a content addressable memory (CAM). The CAM includes a plurality of entries, wherein each entry includes a plurality of column address bits and a plurality of maskable row address bits. When an access address for a memory operation matches an entry of the CAM, the memory system is configured to access the redundant memory array to perform the memory operation.

Memory repair system and method therefor

The dies of a stacked die integrated circuit (IC) employ the address bus to indicate the particular die, or set of dies, targeted by data on a data bus. During manufacture of the stacked die IC, the IC is programmed with information indicating a width of the address bus. During operation, each die addresses the other dies with addresses having the corresponding width based on this programmed information.

Die stack address bus having a programmable width

A memory circuit includes plurality of bit-cells organized in a column, each bit-cell of the plurality is coupled to a first voltage supply terminal and a second voltage supply terminal. A word-line control circuit is coupled to each bit-cell of the plurality by way of a local bit-line. The word-line control circuit is configured to operatively couple the local bit-line with a global bit-line during a read operation. A first voltage generation circuit is coupled to the first voltage supply terminal. The first voltage generation circuit is configured to provide a first reduced voltage at the first voltage supply terminal during a first write operation. A second voltage generation circuit is coupled to the second voltage supply terminal. The second voltage generation circuit is configured to provide a second reduced voltage at the second voltage supply terminal during the first write operation.

Memory circuit having increased write margin and method therefor

A memory circuit includes a plurality of bit-cells organized in a column. Each bit-cell of the plurality is coupled to first and second voltage supply terminals, and first and second bit-lines. A word-line is coupled to a bit-cell of the plurality and configured to receive a first voltage during a first write operation. A first voltage generation circuit is coupled to the first voltage supply terminal and is configured to provide a first reduced voltage during the first write operation. A second voltage generation circuit is coupled to the second voltage supply terminal and is configured to provide a second reduced voltage during the first write operation.

Memory circuit and method for increased write margin

A memory device includes a non-volatile memory (NVM) array and a memory controller. The NVM array has four partitions in which each partition has as plurality of groups of NVM cells. The memory controller that performs a written operation on each of the four partitions in four cycles per group of NVM cells beginning a clock cycle apart in which two of the four clock cycles for the write operation are for an array write that requires a relatively high current and that the array write for each partition overlaps no more than one other array write so that a peak current of all four write operations is no more than twice the peak current of one group. The NVM cells may be magnetic tunnel junctions (MTJs) which have significantly faster written times than typical NVM cells.

Partitioned memory having pipeline writes

A memory system comprises an SRAM array and a NVM array. The SRAM array and NVM array are both organized in rows and columns. The NVM array is directly coupled to the SRAM array. The memory system may also be coupled to a system bus of a data processing system. The number of columns of the NVM array is an integer multiple of the number of columns of the SRAM array, where the integer multiple is greater than one. Column logic is coupled to the SRAM array and to the NVM array. The column logic controls accesses to the SRAM and to the NVM array, and the column logic controls direct data transfers between the SRAM array and the NVM array.

Direct interface between SRAM and non-volatile memory providing space efficiency by matching pitch in both memories

A buffer circuit includes a first capacitor having a first terminal coupled to receive an input signal, a second capacitor having a first terminal coupled to the first terminal of the first capacitor, and a latching portion coupled to a second terminal of the first capacitor and a second terminal of the second capacitor. The latching portion provides an output signal. A first transistor includes a control electrode coupled to receive the output signal, a first current electrode coupled to a first bias voltage supply terminal, and a second current electrode coupled to the second terminal of the second capacitor.

Small signal input buffer

An integrated circuit optical backplane die and associated semiconductor fabrication process are described for forming optical backplane mirror structures for perpendicularly deflecting optical signals out of the plane of the optical backplane die by selectively etching an optical waveguide semiconductor layer () on an optical backplane die wafer using an orientation-dependent anisotropic wet etch process to form a first recess opening () with angled semiconductor sidewall surfaces () on the optical waveguide semiconductor layer, where the angled semiconductor sidewall surfaces () are processed to form an optical backplane mirror () for perpendicularly deflecting optical signals to and from a lateral plane of the optical waveguide semiconductor layer.

Optical backplane mirror

A non-volatile memory includes a first bit cell having a programmable resistive element coupled to a write bit line wherein the programmable resistive element is programmable to one of two resistive states, a resistive element coupled to the programmable resistive element at a circuit node, and a first transistor configured to operate in saturation during a read operation. The first transistor has a control electrode coupled to the circuit node and a first current electrode coupled to a read bit line.

Memory with read circuitry and method of operating

A memory cell includes a single bi-directional resistive memory element (BRME) having a first terminal directly connected to a first power rail and a second terminal coupled to an internal node; and a first transistor having a control electrode coupled to the internal node, and a first current electrode coupled to a first bitline, and a second current electrode coupled to one of a group consisting of: a read wordline and the first power rail.

Non-volatile memory using bi-directional resistive elements

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Austin, TX, United States of America

Perry H Pelley