Cadence Design Systems, Inc.

Yahoo! Inc.

Claritech Corporation

Pero Subasic

Enis Aykut Dengi

Rodney Phelps

Jan O Pedersen

Ashvin Kannan

Chad Carson

Rukmini Iyer

Erick Cantu-Paz

Christopher C LuVogt

Christopher John Leggetter

George Bogdan Arsintescu

David Cho-Lun Ku

Xuejin Wang

Ibraz H Mohammed

Alison Huettner

A method of system design, and more particularly a method of designing systems that achieve a set of performance goals using a hierarchically partitioned system representation wherein performance simulations are performed at multiple levels within the hierarchy and are combined to simulate a system level result in order to reduce the aggregate time required for performance simulation.

Hierarchical system design

The present invention is directed towards systems and methods for predicting a frequency with which an advertisement displayed in response to a query will be selected. The method of the present invention comprises receiving analytics data associated with a display of one or more advertisements in response to one or more queries. One or more features associated with the one or more advertisements displayed in response to the one or more queries are identified. One or more functions are generated for predicting a frequency with which a given advertisement displayed in response to a query will be selected using the analytics data and features associated with the one or more advertisements displayed in response to the one or more queries.

System and method for generating functions to predict the clickability of advertisements

The invention is a method of placement of components and networks (nets), utilized for interconnecting the components, of a circuit layout. The method includes forming for electrical devices, pads (or lands) and networks (nets) of a circuit layout a listing of the positions thereof with respect to one another, connections therebetween and the orientation of each net or subnet thereof in the circuit layout. The thus formed list is processed subject to at least one objective regarding the size of the circuit layout, whereupon a placement of the electrical devices and the pads is determined simultaneously with the placement of the networks.

Placer with wires for RF and analog design

In a method of determining the existence of one or more conflicts in the placement or configuration of circuit objects defining a circuit, a number of constraints is defined, each of which imposes at least one limitation on at least one circuit object. A number of constraint families is then defined, each of which includes a subset of interrelated constraints. For each of a subset of the constraint families, a determination is made if a conflict exists between the constraints thereof. If not, pairs of constraint families are defined from the plurality constraint families. For each of a subset of the pairs of constraint families, a determination is made if a conflict exists between the constraints thereof. If not, the circuit objects defining the circuit are laid out subject to the constraints.

Constraint data management for electronic design automation

Each circuit simulation performed on unique layout of circuit devices generates a design point (DP) that includes device variable values and performance goal values. Circuit models for at least one performance goal are determined as a function of a first subset of the DPs. A performance goal value is determined for each circuit model based on the device variable values obtained from a second subset of the DPs. Errors are determined between the thus determined value of each performance goal and values of the corresponding performance goals obtained from the second subset of the DPs. Input values of device variables are processed with at least one of the circuit models having the smallest error associated therewith to determine therefor a performance goal value. A layout of the circuit devices is generated based on the input device variable values associated with at least one of the thus determined performance goals.

Performance modeling for circuit design

A visualization and data mining technique can be utilized to facilitate analysis of generated sets of design points for an integrated circuit to enable easy and fast understanding of important properties of generated designs. The use of the visualization and data mining technique significantly reduces the time needed for analysis of design space and decision on which design point to choose for implementing into a circuit design.

Circuit design point selection method and apparatus

A technique for analyzing affect in which ambiguity in both emotion and natural language is explicitly represented and processed through fuzzy logic. In particular, textual information is processed to i) isolate a vocabulary of words belonging to an emotion, ii) represent the meaning of each word belonging to that emotion using multiple categories and scalar metrics, iii) compute profiles for text documents based on the categories and scores of their component words, and iv) manipulate the profiles to visualize the texts. The representation vehicle in the system is a set of fuzzy semantic categories (affect categories) followed by their respective centralities (degrees of relatedness between lexicon entries and their various categories) and intensities (representative of the strength of the affect level described by that word) called an affect set. A graphical representation of the affect set can also be used as a tool for decision making.

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Phoenix, AZ, United States of America

Pero Subasic