Globalfoundries Inc.

Globalfoundries U.S. Inc.

Pernell Dongmo

Vibhor Jain

Qizhi Liu

Cameron E Luce

Ramsey M Hazbun

Steven M Shank

John Joseph Pekarik

Anthony K Stamper

John J Ellis-Monaghan

Judson Robert Holt

James William Adkisson

Zhong-Xiang He

Alvin Jose Joseph

Siva P Adusumilli

Rajendran Krishnasamy

Mark Levy

A transistor structure is provided, the structure may be for a high electron mobility transistor (HEMT). The HEMT comprises a channel layer arranged over a substrate, the channel layer may have a top surface. A barrier layer may be arranged over the channel layer. A first opening may be in the barrier layer and extend partially into the channel layer. A first barrier liner may be arranged in the first opening and over the channel layer, the first barrier liner may have a bottom surface. The bottom surface of the first barrier liner may be lower than the top surface of the channel layer.

High electron mobility transistors having barrier liners and integration schemes

The present disclosure relates to semiconductor structures and, more particularly, to an avalanche photodiode and methods of manufacture. The structure includes: a substrate material having a trench with sidewalls and a bottom composed of the substrate material; a first semiconductor material lining the sidewalls and the bottom of the trench; a photosensitive semiconductor material provided on the first semiconductor material; and a third semiconductor material provided on the photosensitive semiconductor material.

Avalanche photodiode

The present disclosure relates to semiconductor structures and, more particularly, to heterojunction bipolar transistors and methods of manufacture. The structure includes: a sub-collector region in a substrate; a collector region above the sub-collector region, the collector region composed of semiconductor material; an intrinsic base region composed of intrinsic base material surrounded by the semiconductor material above the collector region; and an emitter region above the intrinsic base region.

Heterojunction bipolar transistors

Fabrication methods and device structures for a heterojunction bipolar transistor. A trench isolation region is formed that surrounds an active region of semiconductor material, a collector is formed in the active region, and a base layer is deposited that includes a first section over the trench isolation region, a second section over the active region, and a third section over the active region that connects the first section and the second section. An emitter is arranged over the second section of the base layer, and an extrinsic base layer is arranged over the first section of the base layer and the third section of the base layer. The extrinsic base layer includes a first section containing polycrystalline semiconductor material and a second section containing single-crystal semiconductor material. The first and second sections of the extrinsic base layer intersect along an interface that extends over the trench isolation region.

Heterojunction bipolar transistors with an inverted crystalline boundary in the base layer

Device structures and fabrication methods for a bipolar junction transistor. A trench isolation region surrounds an active region that includes a collector. A base layer is arranged over the active region, and a semiconductor layer is arranged on the base layer. The semiconductor layer includes a stepped profile with a first section having a first width adjacent to the base layer and a second section having a second width that is less than the first width. An emitter is arranged on the second section of the semiconductor layer.

Bipolar junction transistors with a self-aligned emitter and base

Structures that integrate airgaps with a field-effect transistor and methods for forming a field-effect transistor with integrated airgaps. A first semiconductor layer is formed on a substrate, and a second semiconductor layer is formed over the first semiconductor layer. A source/drain region of a field-effect transistor is formed in the second semiconductor layer. An airgap is located in the first semiconductor layer, The airgap is arranged in a vertical direction between the source/drain region and the substrate.

Field-effect transistors with airgaps

Fabrication methods and device structures for bipolar junction transistors and heterojunction bipolar transistors. A first dielectric layer is formed and a second dielectric layer is formed on the first dielectric layer. An opening is etched extending vertically through the first dielectric layer and the second dielectric layer. A collector is formed inside the opening. An intrinsic base, which is also formed inside the opening, has a vertical arrangement relative to the collector.

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Essex Junction, VT, United States of America

Pernell Dongmo